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[88.99.136.175]) by smtp.gmail.com with ESMTPSA id i9-20020adfefc9000000b002251c75c09csm12699691wrp.90.2022.08.30.20.09.44 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 30 Aug 2022 20:09:44 -0700 (PDT) From: ci_notify@linaro.org X-Google-Original-From: linaro-infrastructure-errors@lists.linaro.org Date: Wed, 31 Aug 2022 03:09:42 +0000 (UTC) To: Andrew Stubbs Cc: gcc-regression@gcc.gnu.org Message-ID: <739790320.10004.1661915384517@jenkins.jenkins> Subject: [TCWG CI] Regression after gcc: omp-simd-clone: Allow fixed-lane vectors MIME-Version: 1.0 Content-Type: multipart/mixed; boundary="----=_Part_10003_1022939893.1661915383555" X-Jenkins-Job: TCWG Bisect tcwg_gcc_bootstrap/master-aarch64-bootstrap X-Jenkins-Result: SUCCESS List-ID: X-Spam-Status: No, score=-13.5 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_LOTSOFHASH,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP,T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org ------=_Part_10003_1022939893.1661915383555 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable Regression after gcc: omp-simd-clone: Allow fixed-lane vectors: commit f134a25ee8c29646f35f7e466109f6a7f5b9e824 Author: Andrew Stubbs omp-simd-clone: Allow fixed-lane vectors Results changed to -10 0 1 # build_abe bootstrap: # FAILED # First few build errors in logs: # 00:04:21 make[3]: [Makefile:1787: aarch64-unknown-linux-gnu/bits/largefil= e-config.h] Error 1 (ignored) # 00:04:21 make[3]: [Makefile:1788: aarch64-unknown-linux-gnu/bits/largefil= e-config.h] Error 1 (ignored) # 00:09:26 /home/tcwg-buildslave/workspace/tcwg_gnu_13/abe/snapshots/gcc.gi= t~master/gcc/poly-int.h:1295:22: error: comparison of integer expressions o= f different signedness: =E2=80=98const long unsigned int=E2=80=99 and =E2= =80=98const int=E2=80=99 [-Werror=3Dsign-compare] # 00:09:35 make[3]: *** [Makefile:1146: omp-simd-clone.o] Error 1 # 00:26:43 make[2]: *** [Makefile:4979: all-stage2-gcc] Error 2 # 00:26:43 make[1]: *** [Makefile:25558: stage2-bubble] Error 2 # 00:26:43 make: *** [Makefile:1064: all] Error 2 from -10 # true: 0 # build_abe binutils: 1 # build_abe bootstrap: 2 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCT= ION INSTRUCTIONS, AND THE RAW COMMIT. For latest status see comments in https://linaro.atlassian.net/browse/GNU-6= 92 . [GNU-692] Status of basepoints/gcc-13-2290-gf134a25ee8c commit for ci_project tcwg_gc= c_bootstrap: * master-aarch64-bootstrap ** Regression after gcc: omp-simd-clone: Allow fixed-lane vectors: ** commit f134a25ee8c29646f35f7e466109f6a7f5b9e824 ** Author: Andrew Stubbs **=20 ** omp-simd-clone: Allow fixed-lane vectors ** https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-aarch64-boots= trap/12/ Details: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-aarch64= -bootstrap/12/artifact/artifacts/jenkins/mail-body.txt/*view*/ Even more details: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-mast= er-aarch64-bootstrap/12/artifact/artifacts/ First_bad build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master= -aarch64-bootstrap/12/artifact/artifacts/build-f134a25ee8c29646f35f7e466109= f6a7f5b9e824/ Last_good build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master= -aarch64-bootstrap/12/artifact/artifacts/build-1025025b612d632920fe710bb58d= 36e4d43f3220/ Baseline build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-= aarch64-bootstrap/12/artifact/artifacts/build-baseline/ Even more details: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-mast= er-aarch64-bootstrap/12/artifact/artifacts/ Reproduce builds: mkdir investigate-gcc-f134a25ee8c29646f35f7e466109f6a7f5b9e824 cd investigate-gcc-f134a25ee8c29646f35f7e466109f6a7f5b9e824 # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/build-baseline artifacts/build-parameters curl -o artifacts/build-baseline/manifest.sh https://ci.linaro.org/job/tcwg= _gcc_bootstrap-bisect-master-aarch64-bootstrap/12/artifact/artifacts/build-= baseline/manifest.sh --fail curl -o artifacts/build-parameters/manifest.sh https://ci.linaro.org/job/tc= wg_gcc_bootstrap-bisect-master-aarch64-bootstrap/12/artifact/artifacts/buil= d-parameters/manifest.sh --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_gcc_bootstrap-bise= ct-master-aarch64-bootstrap/12/artifact/artifacts/test.sh --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_gnu-build.sh ^^ true %%rr[top_artifacts] artifacts/b= uild-baseline # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ -= -exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach f134a25ee8c29646f35f7e466109f6a7f5b9e824 ../artifacts/test.sh # Reproduce last_good build git checkout --detach 1025025b612d632920fe710bb58d36e4d43f3220 ../artifacts/test.sh cd .. Full commit (up to 1000 lines): commit f134a25ee8c29646f35f7e466109f6a7f5b9e824 Author: Andrew Stubbs Date: Fri Aug 5 13:28:50 2022 +0100 omp-simd-clone: Allow fixed-lane vectors =20 The vecsize_int/vecsize_float has an assumption that all arguments will= use the same bitsize, and vary the number of lanes according to the element= size, but this is inappropriate on targets where the number of lanes is fixed= and the bitsize varies (i.e. amdgcn). =20 With this change the vecsize can be left zero and the vectorization fac= tor will be the same for all types. =20 gcc/ChangeLog: =20 * doc/tm.texi: Regenerate. * omp-simd-clone.cc (simd_clone_adjust_return_type): Allow zero vecsize. (simd_clone_adjust_argument_types): Likewise. * target.def (compute_vecsize_and_simdlen): Document the new vecsize_int and vecsize_float semantics. --- gcc/doc/tm.texi | 3 +++ gcc/omp-simd-clone.cc | 20 +++++++++++++++----- gcc/target.def | 3 +++ 3 files changed, 21 insertions(+), 5 deletions(-) diff --git a/gcc/doc/tm.texi b/gcc/doc/tm.texi index 92bda1a7e14..c3001c6ded9 100644 --- a/gcc/doc/tm.texi +++ b/gcc/doc/tm.texi @@ -6253,6 +6253,9 @@ stores. This hook should set @var{vecsize_mangle}, @var{vecsize_int}, @var{vecsize= _float} fields in @var{simd_clone} structure pointed by @var{clone_info} argument = and also @var{simdlen} field if it was previously 0. +@var{vecsize_mangle} is a marker for the backend only. @var{vecsize_int} a= nd +@var{vecsize_float} should be left zero on targets where the number of lan= es is +not determined by the bitsize (in which case @var{simdlen} is always used)= . The hook should return 0 if SIMD clones shouldn't be emitted, or number of @var{vecsize_mangle} variants that should be emitted. @end deftypefn diff --git a/gcc/omp-simd-clone.cc b/gcc/omp-simd-clone.cc index 58bd68b129b..68ee4c2c3b0 100644 --- a/gcc/omp-simd-clone.cc +++ b/gcc/omp-simd-clone.cc @@ -504,7 +504,10 @@ simd_clone_adjust_return_type (struct cgraph_node *nod= e) veclen =3D node->simdclone->vecsize_int; else veclen =3D node->simdclone->vecsize_float; - veclen =3D exact_div (veclen, GET_MODE_BITSIZE (SCALAR_TYPE_MODE (t))); + if (known_eq (veclen, 0)) + veclen =3D node->simdclone->simdlen; + else + veclen =3D exact_div (veclen, GET_MODE_BITSIZE (SCALAR_TYPE_MODE (t)))= ; if (multiple_p (veclen, node->simdclone->simdlen)) veclen =3D node->simdclone->simdlen; if (POINTER_TYPE_P (t)) @@ -618,8 +621,12 @@ simd_clone_adjust_argument_types (struct cgraph_node *= node) =09 veclen =3D sc->vecsize_int; =09 else =09 veclen =3D sc->vecsize_float; -=09 veclen =3D exact_div (veclen, -=09=09=09 GET_MODE_BITSIZE (SCALAR_TYPE_MODE (parm_type))); +=09 if (known_eq (veclen, 0)) +=09 veclen =3D sc->simdlen; +=09 else +=09 veclen +=09 =3D exact_div (veclen, +=09=09=09 GET_MODE_BITSIZE (SCALAR_TYPE_MODE (parm_type))); =09 if (multiple_p (veclen, sc->simdlen)) =09 veclen =3D sc->simdlen; =09 adj.op =3D IPA_PARAM_OP_NEW; @@ -669,8 +676,11 @@ simd_clone_adjust_argument_types (struct cgraph_node *= node) =09veclen =3D sc->vecsize_int; else =09veclen =3D sc->vecsize_float; - veclen =3D exact_div (veclen, -=09=09=09 GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type))); + if (known_eq (veclen, 0)) +=09veclen =3D sc->simdlen; + else +=09veclen =3D exact_div (veclen, +=09=09=09 GET_MODE_BITSIZE (SCALAR_TYPE_MODE (base_type))); if (multiple_p (veclen, sc->simdlen)) =09veclen =3D sc->simdlen; if (sc->mask_mode !=3D VOIDmode) diff --git a/gcc/target.def b/gcc/target.def index 2a7fa68f83d..4d49ffc2c88 100644 --- a/gcc/target.def +++ b/gcc/target.def @@ -1629,6 +1629,9 @@ DEFHOOK "This hook should set @var{vecsize_mangle}, @var{vecsize_int}, @var{vecsiz= e_float}\n\ fields in @var{simd_clone} structure pointed by @var{clone_info} argument = and also\n\ @var{simdlen} field if it was previously 0.\n\ +@var{vecsize_mangle} is a marker for the backend only. @var{vecsize_int} a= nd\n\ +@var{vecsize_float} should be left zero on targets where the number of lan= es is\n\ +not determined by the bitsize (in which case @var{simdlen} is always used)= .\n\ The hook should return 0 if SIMD clones shouldn't be emitted,\n\ or number of @var{vecsize_mangle} variants that should be emitted.", int, (struct cgraph_node *, struct cgraph_simd_clone *, tree, int), NULL) ------=_Part_10003_1022939893.1661915383555--