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[88.99.136.175]) by smtp.gmail.com with ESMTPSA id n19-20020a05600c4f9300b0037c06fe68casm3962929wmq.44.2022.02.22.16.55.37 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Tue, 22 Feb 2022 16:55:37 -0800 (PST) From: ci_notify@linaro.org X-Google-Original-From: linaro-infrastructure-errors@lists.linaro.org Date: Wed, 23 Feb 2022 00:55:36 +0000 (UTC) To: Christophe Lyon Cc: gcc-regression@gcc.gnu.org Message-ID: <851863563.35.1645577737864@jenkins.jenkins> Subject: [TCWG CI] Regression caused by gcc: arm: Implement auto-vectorized MVE comparisons with vectors of boolean predicates MIME-Version: 1.0 X-Jenkins-Job: TCWG Bisect tcwg_gcc_bootstrap/master-arm-bootstrap X-Jenkins-Result: SUCCESS X-Spam-Status: No, score=-12.8 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, GIT_PATCH_0, KAM_ASCII_DIVIDERS, KAM_LOTSOFHASH, KAM_SHORT, RCVD_IN_DNSWL_NONE, SCC_5_SHORT_WORD_LINES, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Content-Filtered-By: Mailman/MimeDel 2.1.29 X-BeenThere: gcc-regression@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-regression mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Feb 2022 00:55:45 -0000 [TCWG CI] Regression caused by gcc: arm: Implement auto-vectorized MVE comp= arisons with vectors of boolean predicates: commit 91224cf625dc90304bb515a0cc602beed48fe3da Author: Christophe Lyon arm: Implement auto-vectorized MVE comparisons with vectors of boolean = predicates Results regressed to # reset_artifacts: -10 # true: 0 # build_abe binutils: 1 # First few build errors in logs: # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:196:23: error: =E2=80=98mve_const_bool_vec_to= _hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:196:23: error: =E2=80=98mve_const_bool_vec_to= _hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:196:23: error: =E2=80=98mve_const_bool_vec_to= _hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:196:23: error: =E2=80=98mve_const_bool_vec_to= _hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope # 00:01:29 /home/tcwg-buildslave/workspace/tcwg_gnu_3/abe/snapshots/gcc.git= ~master/gcc/config/arm/vfp.md:92:23: error: =E2=80=98mve_const_bool_vec_to_= hi=E2=80=99 was not declared in this scope from # reset_artifacts: -10 # true: 0 # build_abe binutils: 1 # build_abe bootstrap: 2 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCT= ION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_gcc_bootstrap/master-arm-bootstrap First_bad build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master= -arm-bootstrap/11/artifact/artifacts/build-91224cf625dc90304bb515a0cc602bee= d48fe3da/ Last_good build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master= -arm-bootstrap/11/artifact/artifacts/build-884f77b4222289510e1df9db2889b60c= 5df6fcda/ Baseline build: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-master-= arm-bootstrap/11/artifact/artifacts/build-baseline/ Even more details: https://ci.linaro.org/job/tcwg_gcc_bootstrap-bisect-mast= er-arm-bootstrap/11/artifact/artifacts/ Reproduce builds: mkdir investigate-gcc-91224cf625dc90304bb515a0cc602beed48fe3da cd investigate-gcc-91224cf625dc90304bb515a0cc602beed48fe3da # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcw= g_gcc_bootstrap-bisect-master-arm-bootstrap/11/artifact/artifacts/manifests= /build-baseline.sh --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/t= cwg_gcc_bootstrap-bisect-master-arm-bootstrap/11/artifact/artifacts/manifes= ts/build-parameters.sh --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_gcc_bootstrap-bise= ct-master-arm-bootstrap/11/artifact/artifacts/test.sh --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_gnu-build.sh @@ artifacts/manifests/build-baseline.s= h # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ -= -exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach 91224cf625dc90304bb515a0cc602beed48fe3da ../artifacts/test.sh # Reproduce last_good build git checkout --detach 884f77b4222289510e1df9db2889b60c5df6fcda ../artifacts/test.sh cd .. Full commit (up to 1000 lines): commit 91224cf625dc90304bb515a0cc602beed48fe3da Author: Christophe Lyon Date: Wed Oct 13 09:16:27 2021 +0000 arm: Implement auto-vectorized MVE comparisons with vectors of boolean = predicates =20 We make use of qualifier_predicate to describe MVE builtins prototypes, restricting to auto-vectorizable vcmp* and vpsel builtins, as they are exercised by the tests added earlier in the series. =20 Special handling is needed for mve_vpselq because it has a v2di variant, which has no natural VPR.P0 representation: we keep HImode for it. =20 The vector_compare expansion code is updated to use the right VxBI mode instead of HI for the result. =20 We extend the existing thumb2_movhi_vfp and thumb2_movhi_fp16 patterns to use the new MVE_7_HI iterator which covers HI and the new VxBI modes, in conjunction with the new DB constraint for a constant vector of booleans. =20 This patch also adds tests derived from the one provided in PR target/101325: there is a compile-only test because I did not have access to anything that could execute MVE code until recently. I have been able to add an executable test since QEMU supports MVE. =20 Instead of adding arm_v8_1m_mve_hw, I update arm_mve_hw so that it uses add_options_for_arm_v8_1m_mve_fp, like arm_neon_hw does. This ensures arm_mve_hw passes even if the toolchain does not generate MVE code by default. =20 Most of the work of this patch series was carried out while I was working at STMicroelectronics as a Linaro assignee. =20 2022-02-22 Christophe Lyon Richard Sandiford =20 gcc/ PR target/100757 PR target/101325 * config/arm/arm-builtins.cc (BINOP_PRED_UNONE_UNONE_QUALIFIERS= ) (BINOP_PRED_NONE_NONE_QUALIFIERS) (TERNOP_NONE_NONE_NONE_PRED_QUALIFIERS) (TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS): New. * config/arm/arm-protos.h (mve_bool_vec_to_const): New. * config/arm/arm.cc (arm_hard_regno_mode_ok): Handle new VxBI modes. (arm_mode_to_pred_mode): New. (arm_expand_vector_compare): Use the right VxBI mode instead of HI. (arm_expand_vcond): Likewise. (simd_valid_immediate): Handle MODE_VECTOR_BOOL. (mve_bool_vec_to_const): New. (neon_make_constant): Call mve_bool_vec_to_const when needed. * config/arm/arm_mve_builtins.def (vcmpneq_, vcmphiq_, vcmpcsq_= ) (vcmpltq_, vcmpleq_, vcmpgtq_, vcmpgeq_, vcmpeqq_, vcmpneq_f) (vcmpltq_f, vcmpleq_f, vcmpgtq_f, vcmpgeq_f, vcmpeqq_f, vpselq_= u) (vpselq_s, vpselq_f): Use new predicated qualifiers. * config/arm/constraints.md (DB): New. * config/arm/iterators.md (MVE_7, MVE_7_HI): New mode iterators= . (MVE_VPRED, MVE_vpred): New attribute iterators. * config/arm/mve.md (@mve_vcmpq_) (@mve_vcmpq_f, @mve_vpselq_) (@mve_vpselq_f): Use MVE_VPRED instead of HI. (@mve_vpselq_v2di): Define separately. (mov): New expander for VxBI modes. * config/arm/vfp.md (thumb2_movhi_vfp, thumb2_movhi_fp16): Use MVE_7_HI iterator and add support for DB constraint. =20 gcc/testsuite/ PR target/100757 PR target/101325 * gcc.dg/rtl/arm/mve-vxbi.c: New test. * gcc.target/arm/simd/pr101325.c: New. * gcc.target/arm/simd/pr101325-2.c: New. * lib/target-supports.exp (check_effective_target_arm_mve_hw): = Use add_options_for_arm_v8_1m_mve_fp. --- gcc/config/arm/arm-builtins.cc | 25 ++++++++ gcc/config/arm/arm-protos.h | 1 + gcc/config/arm/arm.cc | 56 ++++++++++++++-- gcc/config/arm/arm_mve_builtins.def | 34 +++++----- gcc/config/arm/constraints.md | 6 ++ gcc/config/arm/iterators.md | 6 ++ gcc/config/arm/mve.md | 23 +++++-- gcc/config/arm/vfp.md | 34 ++++++---- gcc/testsuite/gcc.dg/rtl/arm/mve-vxbi.c | 89 ++++++++++++++++++++++= ++++ gcc/testsuite/gcc.target/arm/simd/pr101325-2.c | 19 ++++++ gcc/testsuite/gcc.target/arm/simd/pr101325.c | 14 ++++ gcc/testsuite/lib/target-supports.exp | 3 +- 12 files changed, 268 insertions(+), 42 deletions(-) diff --git a/gcc/config/arm/arm-builtins.cc b/gcc/config/arm/arm-builtins.c= c index 993a2f7b082..1c6b9c986ee 100644 --- a/gcc/config/arm/arm-builtins.cc +++ b/gcc/config/arm/arm-builtins.cc @@ -420,6 +420,12 @@ arm_binop_unone_unone_unone_qualifiers[SIMD_MAX_BUILTI= N_ARGS] #define BINOP_UNONE_UNONE_UNONE_QUALIFIERS \ (arm_binop_unone_unone_unone_qualifiers) =20 +static enum arm_type_qualifiers +arm_binop_pred_unone_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_predicate, qualifier_unsigned, qualifier_unsigned }; +#define BINOP_PRED_UNONE_UNONE_QUALIFIERS \ + (arm_binop_pred_unone_unone_qualifiers) + static enum arm_type_qualifiers arm_binop_unone_none_imm_qualifiers[SIMD_MAX_BUILTIN_ARGS] =3D { qualifier_unsigned, qualifier_none, qualifier_immediate }; @@ -438,6 +444,12 @@ arm_binop_unone_none_none_qualifiers[SIMD_MAX_BUILTIN_= ARGS] #define BINOP_UNONE_NONE_NONE_QUALIFIERS \ (arm_binop_unone_none_none_qualifiers) =20 +static enum arm_type_qualifiers +arm_binop_pred_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_predicate, qualifier_none, qualifier_none }; +#define BINOP_PRED_NONE_NONE_QUALIFIERS \ + (arm_binop_pred_none_none_qualifiers) + static enum arm_type_qualifiers arm_binop_unone_unone_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] =3D { qualifier_unsigned, qualifier_unsigned, qualifier_none }; @@ -509,6 +521,12 @@ arm_ternop_none_none_none_unone_qualifiers[SIMD_MAX_BU= ILTIN_ARGS] #define TERNOP_NONE_NONE_NONE_UNONE_QUALIFIERS \ (arm_ternop_none_none_none_unone_qualifiers) =20 +static enum arm_type_qualifiers +arm_ternop_none_none_none_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_none, qualifier_none, qualifier_none, qualifier_predicat= e }; +#define TERNOP_NONE_NONE_NONE_PRED_QUALIFIERS \ + (arm_ternop_none_none_none_pred_qualifiers) + static enum arm_type_qualifiers arm_ternop_none_none_imm_unone_qualifiers[SIMD_MAX_BUILTIN_ARGS] =3D { qualifier_none, qualifier_none, qualifier_immediate, qualifier_uns= igned }; @@ -528,6 +546,13 @@ arm_ternop_unone_unone_unone_unone_qualifiers[SIMD_MAX= _BUILTIN_ARGS] #define TERNOP_UNONE_UNONE_UNONE_UNONE_QUALIFIERS \ (arm_ternop_unone_unone_unone_unone_qualifiers) =20 +static enum arm_type_qualifiers +arm_ternop_unone_unone_unone_pred_qualifiers[SIMD_MAX_BUILTIN_ARGS] + =3D { qualifier_unsigned, qualifier_unsigned, qualifier_unsigned, + qualifier_predicate }; +#define TERNOP_UNONE_UNONE_UNONE_PRED_QUALIFIERS \ + (arm_ternop_unone_unone_unone_pred_qualifiers) + static enum arm_type_qualifiers arm_ternop_none_none_none_none_qualifiers[SIMD_MAX_BUILTIN_ARGS] =3D { qualifier_none, qualifier_none, qualifier_none, qualifier_none }; diff --git a/gcc/config/arm/arm-protos.h b/gcc/config/arm/arm-protos.h index 881c72c988b..f2f7ca6c23c 100644 --- a/gcc/config/arm/arm-protos.h +++ b/gcc/config/arm/arm-protos.h @@ -101,6 +101,7 @@ extern char *neon_output_shift_immediate (const char *,= char, rtx *, =09=09=09=09=09 machine_mode, int, bool); extern void neon_pairwise_reduce (rtx, rtx, machine_mode, =09=09=09=09 rtx (*) (rtx, rtx, rtx)); +extern rtx mve_bool_vec_to_const (rtx const_vec); extern rtx neon_make_constant (rtx, bool generate =3D true); extern tree arm_builtin_vectorized_function (unsigned int, tree, tree); extern void neon_expand_vector_init (rtx, rtx); diff --git a/gcc/config/arm/arm.cc b/gcc/config/arm/arm.cc index 8d7f095b59b..df43c670b05 100644 --- a/gcc/config/arm/arm.cc +++ b/gcc/config/arm/arm.cc @@ -12802,7 +12802,10 @@ simd_valid_immediate (rtx op, machine_mode mode, i= nt inverse, innersize =3D GET_MODE_UNIT_SIZE (mode); =20 /* Only support 128-bit vectors for MVE. */ - if (TARGET_HAVE_MVE && (!vector || n_elts * innersize !=3D 16)) + if (TARGET_HAVE_MVE + && (!vector +=09 || (GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BOOL) +=09 || n_elts * innersize !=3D 16)) return -1; =20 /* Vectors of float constants. */ @@ -13167,6 +13170,29 @@ neon_vdup_constant (rtx vals, bool generate) return gen_vec_duplicate (mode, x); } =20 +/* Return a HI representation of CONST_VEC suitable for MVE predicates. *= / +rtx +mve_bool_vec_to_const (rtx const_vec) +{ + int n_elts =3D GET_MODE_NUNITS ( GET_MODE (const_vec)); + int repeat =3D 16 / n_elts; + int i; + int hi_val =3D 0; + + for (i =3D 0; i < n_elts; i++) + { + rtx el =3D CONST_VECTOR_ELT (const_vec, i); + unsigned HOST_WIDE_INT elpart; + + gcc_assert (CONST_INT_P (el)); + elpart =3D INTVAL (el); + + for (int j =3D 0; j < repeat; j++) +=09hi_val |=3D elpart << (i * repeat + j); + } + return gen_int_mode (hi_val, HImode); +} + /* Return a non-NULL RTX iff VALS, which is a PARALLEL containing only constants (for vec_init) or CONST_VECTOR, can be effeciently loaded into a register. @@ -13207,6 +13233,8 @@ neon_make_constant (rtx vals, bool generate) && simd_immediate_valid_for_move (const_vec, mode, NULL, NULL)) /* Load using VMOV. On Cortex-A8 this takes one cycle. */ return const_vec; + else if (TARGET_HAVE_MVE && (GET_MODE_CLASS (mode) =3D=3D MODE_VECTOR_BO= OL)) + return mve_bool_vec_to_const (const_vec); else if ((target =3D neon_vdup_constant (vals, generate)) !=3D NULL_RTX) /* Loaded using VDUP. On Cortex-A8 the VDUP takes one NEON pipeline cycle; creating the constant takes one or two ARM @@ -25365,7 +25393,10 @@ arm_hard_regno_mode_ok (unsigned int regno, machin= e_mode mode) return false; =20 if (IS_VPR_REGNUM (regno)) - return mode =3D=3D HImode; + return mode =3D=3D HImode + || mode =3D=3D V16BImode + || mode =3D=3D V8BImode + || mode =3D=3D V4BImode; =20 if (TARGET_THUMB1) /* For the Thumb we only allow values bigger than SImode in @@ -31053,6 +31084,19 @@ arm_split_atomic_op (enum rtx_code code, rtx old_o= ut, rtx new_out, rtx mem, arm_post_atomic_barrier (model); } =0C +/* Return the mode for the MVE vector of predicates corresponding to MODE.= */ +machine_mode +arm_mode_to_pred_mode (machine_mode mode) +{ + switch (GET_MODE_NUNITS (mode)) + { + case 16: return V16BImode; + case 8: return V8BImode; + case 4: return V4BImode; + } + gcc_unreachable (); +} + /* Expand code to compare vectors OP0 and OP1 using condition CODE. If CAN_INVERT, store either the result or its inverse in TARGET and return true if TARGET contains the inverse. If !CAN_INVERT, @@ -31136,7 +31180,7 @@ arm_expand_vector_compare (rtx target, rtx_code cod= e, rtx op0, rtx op1, =09 if (vcond_mve) =09 vpr_p0 =3D target; =09 else -=09 vpr_p0 =3D gen_reg_rtx (HImode); +=09 vpr_p0 =3D gen_reg_rtx (arm_mode_to_pred_mode (cmp_mode)); =20 =09 switch (GET_MODE_CLASS (cmp_mode)) =09 { @@ -31178,7 +31222,7 @@ arm_expand_vector_compare (rtx target, rtx_code cod= e, rtx op0, rtx op1, =09 if (vcond_mve) =09 vpr_p0 =3D target; =09 else -=09 vpr_p0 =3D gen_reg_rtx (HImode); +=09 vpr_p0 =3D gen_reg_rtx (arm_mode_to_pred_mode (cmp_mode)); =20 =09 emit_insn (gen_mve_vcmpq (code, cmp_mode, vpr_p0, op0, force_reg (cmp= _mode, op1))); =09 if (!vcond_mve) @@ -31205,7 +31249,7 @@ arm_expand_vector_compare (rtx target, rtx_code cod= e, rtx op0, rtx op1, =09 if (vcond_mve) =09 vpr_p0 =3D target; =09 else -=09 vpr_p0 =3D gen_reg_rtx (HImode); +=09 vpr_p0 =3D gen_reg_rtx (arm_mode_to_pred_mode (cmp_mode)); =20 =09 emit_insn (gen_mve_vcmpq (swap_condition (code), cmp_mode, vpr_p0, fo= rce_reg (cmp_mode, op1), op0)); =09 if (!vcond_mve) @@ -31258,7 +31302,7 @@ arm_expand_vcond (rtx *operands, machine_mode cmp_r= esult_mode) if (TARGET_HAVE_MVE) { vcond_mve=3Dtrue; - mask =3D gen_reg_rtx (HImode); + mask =3D gen_reg_rtx (arm_mode_to_pred_mode (cmp_result_mode)); } else mask =3D gen_reg_rtx (cmp_result_mode); diff --git a/gcc/config/arm/arm_mve_builtins.def b/gcc/config/arm/arm_mve_b= uiltins.def index c3ae40765fe..44b41eab4c5 100644 --- a/gcc/config/arm/arm_mve_builtins.def +++ b/gcc/config/arm/arm_mve_builtins.def @@ -89,7 +89,7 @@ VAR3 (BINOP_UNONE_UNONE_IMM, vshrq_n_u, v16qi, v8hi, v4si= ) VAR3 (BINOP_NONE_NONE_IMM, vshrq_n_s, v16qi, v8hi, v4si) VAR1 (BINOP_NONE_NONE_UNONE, vaddlvq_p_s, v4si) VAR1 (BINOP_UNONE_UNONE_UNONE, vaddlvq_p_u, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpneq_, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_NONE, vshlq_s, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_NONE, vshlq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vsubq_u, v16qi, v8hi, v4si) @@ -117,9 +117,9 @@ VAR3 (BINOP_UNONE_UNONE_UNONE, vhsubq_n_u, v16qi, v8hi,= v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vhaddq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, veorq_u, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmphiq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmphiq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_UNONE_UNONE, vcmpcsq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vcmpcsq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vbicq_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_UNONE, vandq_u, v16qi, v8hi, v4si) @@ -143,15 +143,15 @@ VAR3 (BINOP_UNONE_UNONE_IMM, vshlq_n_u, v16qi, v8hi, = v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vrshrq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_UNONE_IMM, vqshlq_n_u, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpneq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpltq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpltq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpleq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpleq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgtq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpgeq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_, v16qi, v8hi, v4si) -VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) +VAR3 (BINOP_PRED_NONE_NONE, vcmpeqq_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_, v16qi, v8hi, v4si) VAR3 (BINOP_UNONE_NONE_IMM, vqshluq_n_s, v16qi, v8hi, v4si) VAR3 (BINOP_NONE_NONE_UNONE, vaddvq_p_s, v16qi, v8hi, v4si) @@ -219,17 +219,17 @@ VAR2 (BINOP_UNONE_UNONE_IMM, vshllbq_n_u, v16qi, v8hi= ) VAR2 (BINOP_UNONE_UNONE_IMM, vorrq_n_u, v8hi, v4si) VAR2 (BINOP_UNONE_UNONE_IMM, vbicq_n_u, v8hi, v4si) VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpneq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpneq_f, v8hf, v4sf) VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpltq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpltq_f, v8hf, v4sf) VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpleq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpleq_f, v8hf, v4sf) VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgtq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgtq_f, v8hf, v4sf) VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpgeq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpgeq_f, v8hf, v4sf) VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_n_f, v8hf, v4sf) -VAR2 (BINOP_UNONE_NONE_NONE, vcmpeqq_f, v8hf, v4sf) +VAR2 (BINOP_PRED_NONE_NONE, vcmpeqq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vsubq_f, v8hf, v4sf) VAR2 (BINOP_NONE_NONE_NONE, vqmovntq_s, v8hi, v4si) VAR2 (BINOP_NONE_NONE_NONE, vqmovnbq_s, v8hi, v4si) @@ -295,8 +295,8 @@ VAR2 (TERNOP_UNONE_UNONE_NONE_UNONE, vcvtaq_m_u, v8hi, = v4si) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vcvtaq_m_s, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_IMM, vshlcq_vec_u, v16qi, v8hi, v4si) VAR3 (TERNOP_NONE_NONE_UNONE_IMM, vshlcq_vec_s, v16qi, v8hi, v4si) -VAR4 (TERNOP_UNONE_UNONE_UNONE_UNONE, vpselq_u, v16qi, v8hi, v4si, v2di) -VAR4 (TERNOP_NONE_NONE_NONE_UNONE, vpselq_s, v16qi, v8hi, v4si, v2di) +VAR4 (TERNOP_UNONE_UNONE_UNONE_PRED, vpselq_u, v16qi, v8hi, v4si, v2di) +VAR4 (TERNOP_NONE_NONE_NONE_PRED, vpselq_s, v16qi, v8hi, v4si, v2di) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vrev64q_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmvnq_m_u, v16qi, v8hi, v4si) VAR3 (TERNOP_UNONE_UNONE_UNONE_UNONE, vmlasq_n_u, v16qi, v8hi, v4si) @@ -426,7 +426,7 @@ VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev64q_m_f, v8hf, v= 4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vrev32q_m_s, v16qi, v8hi) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovntq_m_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vqmovnbq_m_s, v8hi, v4si) -VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vpselq_f, v8hf, v4sf) +VAR2 (TERNOP_NONE_NONE_NONE_PRED, vpselq_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vnegq_m_f, v8hf, v4sf) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovntq_m_s, v8hi, v4si) VAR2 (TERNOP_NONE_NONE_NONE_UNONE, vmovnbq_m_s, v8hi, v4si) diff --git a/gcc/config/arm/constraints.md b/gcc/config/arm/constraints.md index 1920004b450..2b411b0cb0f 100644 --- a/gcc/config/arm/constraints.md +++ b/gcc/config/arm/constraints.md @@ -312,6 +312,12 @@ (and (match_code "const_vector") (match_test "(TARGET_NEON || TARGET_HAVE_MVE) && op =3D=3D CONST0_RT= X (mode)"))) =20 +(define_constraint "DB" + "@internal + In ARM/Thumb-2 state with MVE a constant vector of booleans." + (and (match_code "const_vector") + (match_test "TARGET_HAVE_MVE && GET_MODE_CLASS (mode) =3D=3D MODE_VE= CTOR_BOOL"))) + (define_constraint "Da" "@internal In ARM/Thumb-2 state a const_int, const_double or const_vector that can diff --git a/gcc/config/arm/iterators.md b/gcc/config/arm/iterators.md index 8202c27cc82..37cf7971be8 100644 --- a/gcc/config/arm/iterators.md +++ b/gcc/config/arm/iterators.md @@ -272,6 +272,8 @@ (define_mode_iterator MVE_2 [V16QI V8HI V4SI]) (define_mode_iterator MVE_5 [V8HI V4SI]) (define_mode_iterator MVE_6 [V8HI V4SI]) +(define_mode_iterator MVE_7 [V16BI V8BI V4BI]) +(define_mode_iterator MVE_7_HI [HI V16BI V8BI V4BI]) =20 ;;------------------------------------------------------------------------= ---- ;; Code iterators @@ -946,6 +948,10 @@ =09=09=09 (V8HF "u16") (V4SF "32")]) (define_mode_attr earlyclobber_32 [(V16QI "=3Dw") (V8HI "=3Dw") (V4SI "=3D= &w") =09=09=09=09=09=09(V8HF "=3Dw") (V4SF "=3D&w")]) +(define_mode_attr MVE_VPRED [(V16QI "V16BI") (V8HI "V8BI") (V4SI "V4BI") + (V2DI "HI") (V8HF "V8BI") (V4SF "V4BI")]) +(define_mode_attr MVE_vpred [(V16QI "v16bi") (V8HI "v8bi") (V4SI "v4bi") + (V2DI "hi") (V8HF "v8bi") (V4SF "v4bi")]) =20 ;;------------------------------------------------------------------------= ---- ;; Code attributes diff --git a/gcc/config/arm/mve.md b/gcc/config/arm/mve.md index 5c3b34dce3a..983aa10e652 100644 --- a/gcc/config/arm/mve.md +++ b/gcc/config/arm/mve.md @@ -839,8 +839,8 @@ ;; (define_insn "@mve_vcmpq_" [ - (set (match_operand:HI 0 "vpr_register_operand" "=3DUp") -=09(MVE_COMPARISONS:HI (match_operand:MVE_2 1 "s_register_operand" "w") + (set (match_operand: 0 "vpr_register_operand" "=3DUp") +=09(MVE_COMPARISONS: (match_operand:MVE_2 1 "s_register_operand= " "w") =09=09 (match_operand:MVE_2 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE" @@ -1929,8 +1929,8 @@ ;; (define_insn "@mve_vcmpq_f" [ - (set (match_operand:HI 0 "vpr_register_operand" "=3DUp") -=09(MVE_FP_COMPARISONS:HI (match_operand:MVE_0 1 "s_register_operand" "w") + (set (match_operand: 0 "vpr_register_operand" "=3DUp") +=09(MVE_FP_COMPARISONS: (match_operand:MVE_0 1 "s_register_oper= and" "w") =09=09=09 (match_operand:MVE_0 2 "s_register_operand" "w"))) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -3324,7 +3324,7 @@ (set (match_operand:MVE_1 0 "s_register_operand" "=3Dw") =09(unspec:MVE_1 [(match_operand:MVE_1 1 "s_register_operand" "w") =09=09 (match_operand:MVE_1 2 "s_register_operand" "w") -=09=09 (match_operand:HI 3 "vpr_register_operand" "Up")] +=09=09 (match_operand: 3 "vpr_register_operand" "Up")] =09 VPSELQ)) ] "TARGET_HAVE_MVE" @@ -4419,7 +4419,7 @@ (set (match_operand:MVE_0 0 "s_register_operand" "=3Dw") =09(unspec:MVE_0 [(match_operand:MVE_0 1 "s_register_operand" "w") =09=09 (match_operand:MVE_0 2 "s_register_operand" "w") -=09=09 (match_operand:HI 3 "vpr_register_operand" "Up")] +=09=09 (match_operand: 3 "vpr_register_operand" "Up")] =09 VPSELQ_F)) ] "TARGET_HAVE_MVE && TARGET_HAVE_MVE_FLOAT" @@ -10516,3 +10516,14 @@ "vldr.\t%q0, %E1" [(set_attr "type" "mve_load")] ) + +;; Expander for VxBI moves +(define_expand "mov" + [(set (match_operand:MVE_7 0 "nonimmediate_operand") + (match_operand:MVE_7 1 "general_operand"))] + "TARGET_HAVE_MVE" + { + if (!register_operand (operands[0], mode)) + operands[1] =3D force_reg (mode, operands[1]); + } +) diff --git a/gcc/config/arm/vfp.md b/gcc/config/arm/vfp.md index f5ccb92d097..f00d1cad3e9 100644 --- a/gcc/config/arm/vfp.md +++ b/gcc/config/arm/vfp.md @@ -73,21 +73,26 @@ =20 (define_insn "*thumb2_movhi_vfp" [(set - (match_operand:HI 0 "nonimmediate_operand" + (match_operand:MVE_7_HI 0 "nonimmediate_operand" "=3Drk, r, l, r, m, r, *t, r, *t, Up, r") - (match_operand:HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + (match_operand:MVE_7_HI 1 "general_operand" + "rk, IDB, Py, n, r, m, r, *t, *t, r, Up"))] "TARGET_THUMB2 && TARGET_VFP_BASE && !TARGET_VFP_FP16INST - && (register_operand (operands[0], HImode) - || register_operand (operands[1], HImode))" + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" { switch (which_alternative) { case 0: - case 1: case 2: return "mov%?\t%0, %1\t%@ movhi"; + case 1: + if (GET_MODE_CLASS (GET_MODE (operands[1])) =3D=3D MODE_VECTOR_BOOL) + operands[1] =3D mve_const_bool_vec_to_hi (operands[1]); + else + operands[1] =3D gen_lowpart (HImode, operands[1]); + return "mov%?\t%0, %1\t%@ movhi"; case 3: return "movw%?\t%0, %L1\t%@ movhi"; case 4: @@ -173,20 +178,25 @@ =20 (define_insn "*thumb2_movhi_fp16" [(set - (match_operand:HI 0 "nonimmediate_operand" + (match_operand:MVE_7_HI 0 "nonimmediate_operand" "=3Drk, r, l, r, m, r, *t, r, *t, Up, r") - (match_operand:HI 1 "general_operand" - "rk, I, Py, n, r, m, r, *t, *t, r, Up"))] + (match_operand:MVE_7_HI 1 "general_operand" + "rk, IDB, Py, n, r, m, r, *t, *t, r, Up"))] "TARGET_THUMB2 && (TARGET_VFP_FP16INST || TARGET_HAVE_MVE) - && (register_operand (operands[0], HImode) - || register_operand (operands[1], HImode))" + && (register_operand (operands[0], mode) + || register_operand (operands[1], mode))" { switch (which_alternative) { case 0: - case 1: case 2: return "mov%?\t%0, %1\t%@ movhi"; + case 1: + if (GET_MODE_CLASS (GET_MODE (operands[1])) =3D=3D MODE_VECTOR_BOOL) + operands[1] =3D mve_const_bool_vec_to_hi (operands[1]); + else + operands[1] =3D gen_lowpart (HImode, operands[1]); + return "mov%?\t%0, %1\t%@ movhi"; case 3: return "movw%?\t%0, %L1\t%@ movhi"; case 4: diff --git a/gcc/testsuite/gcc.dg/rtl/arm/mve-vxbi.c b/gcc/testsuite/gcc.dg= /rtl/arm/mve-vxbi.c new file mode 100644 index 00000000000..093283ed43c --- /dev/null +++ b/gcc/testsuite/gcc.dg/rtl/arm/mve-vxbi.c @@ -0,0 +1,89 @@ +/* { dg-do compile { target arm*-*-* } } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O2" } */ + +void __RTL (startwith ("ira")) foo (void *ptr) +{ + (function "foo" + (param "ptr" + (DECL_RTL (reg/v:SI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg:SI r0 [ ptr ])) + ) ;; param "n" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 5 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 7 (set (reg:V4BI <1>) +=09 (const_vector:V4BI [(const_int 1) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 1)])) (nil)) + (insn 8 (set (mem:V4BI (reg:SI <0>) [1 ptr+0 S2 A16]) (reg:V4BI <1>))= ) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} + +void __RTL (startwith ("ira")) foo2 (void *ptr) +{ + (function "foo" + (param "ptr" + (DECL_RTL (reg/v:SI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg:SI r0 [ ptr ])) + ) ;; param "n" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 5 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 7 (set (reg:V8BI <1>) +=09 (const_vector:V8BI [(const_int 1) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 1) +=09=09=09=09 (const_int 1) +=09=09=09=09 (const_int 1) +=09=09=09=09 (const_int 1) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 1)])) (nil)) + (insn 8 (set (mem:V8BI (reg:SI <0>) [1 ptr+0 S2 A16]) (reg:V8BI <1>))= ) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} + +void __RTL (startwith ("ira")) foo3 (void *ptr) +{ + (function "foo" + (param "ptr" + (DECL_RTL (reg/v:SI <0> [ ptr ])) + (DECL_RTL_INCOMING (reg:SI r0 [ ptr ])) + ) ;; param "n" + (insn-chain + (block 2 + (edge-from entry (flags "FALLTHRU")) + (cnote 5 [bb 2] NOTE_INSN_BASIC_BLOCK) + (insn 7 (set (reg:V16BI <1>) +=09 (const_vector:V16BI [(const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0) +=09=09=09=09 (const_int 0)])) (nil)) + (insn 8 (set (mem:V16BI (reg:SI <0>) [1 ptr+0 S2 A16]) (reg:V16BI <1>= ))) + (edge-to exit (flags "FALLTHRU")) + ) ;; block 2 + ) ;; insn-chain + ) ;; function +} diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c b/gcc/testsuite= /gcc.target/arm/simd/pr101325-2.c new file mode 100644 index 00000000000..355f6473a00 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr101325-2.c @@ -0,0 +1,19 @@ +/* { dg-do run } */ +/* { dg-require-effective-target arm_mve_hw } */ +/* { dg-options "-O3" } */ +/* { dg-add-options arm_v8_1m_mve } */ + +#include + + +__attribute((noipa)) +unsigned foo(int8x16_t v, int8x16_t w) +{ + return vcmpeqq (v, w); +} + +int main(void) +{ + if (foo (vdupq_n_s8(0), vdupq_n_s8(0)) !=3D 0xffffU) + __builtin_abort (); +} diff --git a/gcc/testsuite/gcc.target/arm/simd/pr101325.c b/gcc/testsuite/g= cc.target/arm/simd/pr101325.c new file mode 100644 index 00000000000..4cb2513da87 --- /dev/null +++ b/gcc/testsuite/gcc.target/arm/simd/pr101325.c @@ -0,0 +1,14 @@ +/* { dg-do compile } */ +/* { dg-require-effective-target arm_v8_1m_mve_ok } */ +/* { dg-add-options arm_v8_1m_mve } */ +/* { dg-additional-options "-O3" } */ + +#include + +unsigned foo(int8x16_t v, int8x16_t w) +{ + return vcmpeqq (v, w); +} +/* { dg-final { scan-assembler {\tvcmp.i8 eq} } } */ +/* { dg-final { scan-assembler {\tvmrs\tr[0-9]+, P0} } } */ +/* { dg-final { scan-assembler {\tuxth} } } */ diff --git a/gcc/testsuite/lib/target-supports.exp b/gcc/testsuite/lib/targ= et-supports.exp index 9a969bfbd17..972400f3451 100644 --- a/gcc/testsuite/lib/target-supports.exp +++ b/gcc/testsuite/lib/target-supports.exp @@ -5038,6 +5038,7 @@ proc check_effective_target_arm_cmse_hw { } { =09} } "-mcmse"] } + # Return 1 if the target supports executing MVE instructions, 0 # otherwise. =20 @@ -5053,7 +5054,7 @@ proc check_effective_target_arm_mve_hw {} { =09 : "0" (a), "r" (b)); =09 return (a !=3D 2); =09} - } ""] + } [add_options_for_arm_v8_1m_mve_fp ""]] } =20 # Return 1 if this is an ARM target where ARMv8-M Security Extensions with >>From hjl@sc.intel.com Wed Feb 23 10:04:40 2022 Return-Path: X-Original-To: gcc-regression@gcc.gnu.org Delivered-To: gcc-regression@gcc.gnu.org Received: from mga06.intel.com (mga06.intel.com [134.134.136.31]) by sourceware.org (Postfix) with ESMTPS id EC534385DC0B for ; Wed, 23 Feb 2022 10:04:38 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org EC534385DC0B X-IronPort-AV: E=McAfee;i="6200,9189,10266"; a="312644651" X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="312644651" Received: from fmsmga006.fm.intel.com ([10.253.24.20]) by orsmga104.jf.intel.com with ESMTP/TLS/ECDHE-RSA-AES256-GCM-SHA384; 23 Feb 2022 02:04:37 -0800 X-ExtLoop1: 1 X-IronPort-AV: E=Sophos;i="5.88,390,1635231600"; d="scan'208";a="776621330" Received: from scymds01.sc.intel.com ([10.148.94.138]) by fmsmga006.fm.intel.com with ESMTP; 23 Feb 2022 02:04:37 -0800 Received: from gnu-skl-2.sc.intel.com (gnu-skl-2.sc.intel.com [172.25.33.230]) by scymds01.sc.intel.com with ESMTP id 21NA4VkF023806; Wed, 23 Feb 2022 02:04:31 -0800 Received: by gnu-skl-2.sc.intel.com (Postfix, from userid 1000) id 2666E3C002D; Wed, 23 Feb 2022 02:04:31 -0800 (PST) Date: Wed, 23 Feb 2022 02:04:31 -0800 To: skpgkp2@gmail.com, hjl.tools@gmail.com, gcc-regression@gcc.gnu.org Subject: Regressions on master at commit r12-7355 vs commit r12-7315 on Linux/x86_64 User-Agent: Heirloom mailx 12.5 7/5/10 MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-Id: <20220223100431.2666E3C002D@gnu-skl-2.sc.intel.com> From: "H.J. Lu" X-Spam-Status: No, score=-3465.9 required=5.0 tests=BAYES_00, KAM_DMARC_STATUS, KAM_LAZY_DOMAIN_SECURITY, KAM_NUMSUBJECT, SPF_HELO_NONE, SPF_NONE, TXREP, T_SCC_BODY_TEXT_LINE autolearn=no autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-regression@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-regression mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Wed, 23 Feb 2022 10:04:40 -0000 New failures: FAIL: g++.dg/modules/xtreme-header-3_b.C -std=c++2a (internal compiler error: in hashtab_chk_error, at hash-table.cc:137) FAIL: g++.dg/modules/xtreme-header-3_b.C -std=c++2a (test for excess errors) New passes: