[TCWG CI] Regression caused by gcc: Add new constant data structure.: commit c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba Author: Michael Meissner Add new constant data structure. Results regressed to # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard: -8 # build_abe newlib: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard: -5 # benchmark -- -Os_mthumb artifacts/build-c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba/results_id: 1 from # reset_artifacts: -10 # build_abe binutils: -9 # build_abe stage1 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard: -8 # build_abe newlib: -6 # build_abe stage2 -- --set gcc_override_configure=--disable-libsanitizer --set gcc_override_configure=--disable-multilib --set gcc_override_configure=--with-cpu=cortex-m4 --set gcc_override_configure=--with-mode=thumb --set gcc_override_configure=--with-float=hard: -5 # benchmark -- -Os_mthumb artifacts/build-baseline/results_id: 1 THIS IS THE END OF INTERESTING STUFF. BELOW ARE LINKS TO BUILDS, REPRODUCTION INSTRUCTIONS, AND THE RAW COMMIT. This commit has regressed these CI configurations: - tcwg_bmk_gnu_eabi_stm32/gnu_eabi-master-arm_eabi-coremark-Os First_bad build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/build-c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba/ Last_good build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/build-71cc9b8c39148d19a8043b74ca8b6b4e8b8072ca/ Baseline build: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/build-baseline/ Even more details: https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/ Reproduce builds: mkdir investigate-gcc-c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba cd investigate-gcc-c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba # Fetch scripts git clone https://git.linaro.org/toolchain/jenkins-scripts # Fetch manifests and test.sh script mkdir -p artifacts/manifests curl -o artifacts/manifests/build-baseline.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/manifests/build-baseline.sh --fail curl -o artifacts/manifests/build-parameters.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/manifests/build-parameters.sh --fail curl -o artifacts/test.sh https://ci.linaro.org/job/tcwg_bmk_ci_gnu_eabi-bisect-tcwg_bmk_stm32-gnu_eabi-master-arm_eabi-coremark-Os/14/artifact/artifacts/test.sh --fail chmod +x artifacts/test.sh # Reproduce the baseline build (build all pre-requisites) ./jenkins-scripts/tcwg_bmk-build.sh @@ artifacts/manifests/build-baseline.sh # Save baseline build state (which is then restored in artifacts/test.sh) mkdir -p ./bisect rsync -a --del --delete-excluded --exclude /bisect/ --exclude /artifacts/ --exclude /gcc/ ./ ./bisect/baseline/ cd gcc # Reproduce first_bad build git checkout --detach c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba ../artifacts/test.sh # Reproduce last_good build git checkout --detach 71cc9b8c39148d19a8043b74ca8b6b4e8b8072ca ../artifacts/test.sh cd .. Full commit (up to 1000 lines): commit c6756b3bc1d2af1c8e86f0ad1711e9b9134520ba Author: Michael Meissner Date: Wed Dec 15 00:56:25 2021 -0500 Add new constant data structure. This patch provides the data structure and function to convert a CONST_INT, CONST_DOUBLE, CONST_VECTOR, or VEC_DUPLICATE of a constant) to an array of bytes, half-words, words, and double words that can be loaded into a 128-bit vector register. The next patches will use this data structure to generate code that generates load of the vector/floating point registers using the XXSPLTIDP, XXSPLTIW, and LXVKQ instructions that were added in power10. 2021-12-15 Michael Meissner gcc/ * config/rs6000/rs6000-protos.h (VECTOR_128BIT_BITS): New macro. (VECTOR_128BIT_BYTES): Likewise. (VECTOR_128BIT_HALF_WORDS): Likewise. (VECTOR_128BIT_WORDS): Likewise. (VECTOR_128BIT_DOUBLE_WORDS): Likewise. (vec_const_128bit_type): New structure type. (vec_const_128bit_to_bytes): New declaration. * config/rs6000/rs6000.c (constant_int_to_128bit_vector): New helper function. (constant_fp_to_128bit_vector): New helper function. (vec_const_128bit_to_bytes): New function. --- gcc/config/rs6000/rs6000-protos.h | 28 +++++ gcc/config/rs6000/rs6000.c | 253 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 281 insertions(+) diff --git a/gcc/config/rs6000/rs6000-protos.h b/gcc/config/rs6000/rs6000-protos.h index c01ae005d0b..81345d80952 100644 --- a/gcc/config/rs6000/rs6000-protos.h +++ b/gcc/config/rs6000/rs6000-protos.h @@ -222,6 +222,34 @@ address_is_prefixed (rtx addr, return (iform == INSN_FORM_PREFIXED_NUMERIC || iform == INSN_FORM_PCREL_LOCAL); } + +/* Functions and data structures relating to 128-bit constants that are + converted to byte, half-word, word, and double-word values. All fields are + kept in big endian order. We also convert scalar values to 128-bits if they + are going to be loaded into vector registers. */ +#define VECTOR_128BIT_BITS 128 +#define VECTOR_128BIT_BYTES (128 / 8) +#define VECTOR_128BIT_HALF_WORDS (128 / 16) +#define VECTOR_128BIT_WORDS (128 / 32) +#define VECTOR_128BIT_DOUBLE_WORDS (128 / 64) + +typedef struct { + /* Constant as various sized items. */ + unsigned HOST_WIDE_INT double_words[VECTOR_128BIT_DOUBLE_WORDS]; + unsigned int words[VECTOR_128BIT_WORDS]; + unsigned short half_words[VECTOR_128BIT_HALF_WORDS]; + unsigned char bytes[VECTOR_128BIT_BYTES]; + + unsigned original_size; /* Constant size before splat. */ + bool fp_constant_p; /* Is the constant floating point? */ + bool all_double_words_same; /* Are the double words all equal? */ + bool all_words_same; /* Are the words all equal? */ + bool all_half_words_same; /* Are the half words all equal? */ + bool all_bytes_same; /* Are the bytes all equal? */ +} vec_const_128bit_type; + +extern bool vec_const_128bit_to_bytes (rtx, machine_mode, + vec_const_128bit_type *); #endif /* RTX_CODE */ #ifdef TREE_CODE diff --git a/gcc/config/rs6000/rs6000.c b/gcc/config/rs6000/rs6000.c index 4481ba57ed7..819314d9fe9 100644 --- a/gcc/config/rs6000/rs6000.c +++ b/gcc/config/rs6000/rs6000.c @@ -28334,6 +28334,259 @@ rs6000_output_addr_vec_elt (FILE *file, int value) fprintf (file, "\n"); } + +/* Copy an integer constant to the vector constant structure. */ + +static void +constant_int_to_128bit_vector (rtx op, + machine_mode mode, + size_t byte_num, + vec_const_128bit_type *info) +{ + unsigned HOST_WIDE_INT uvalue = UINTVAL (op); + unsigned bitsize = GET_MODE_BITSIZE (mode); + + for (int shift = bitsize - 8; shift >= 0; shift -= 8) + info->bytes[byte_num++] = (uvalue >> shift) & 0xff; +} + +/* Copy a floating point constant to the vector constant structure. */ + +static void +constant_fp_to_128bit_vector (rtx op, + machine_mode mode, + size_t byte_num, + vec_const_128bit_type *info) +{ + unsigned bitsize = GET_MODE_BITSIZE (mode); + unsigned num_words = bitsize / 32; + const REAL_VALUE_TYPE *rtype = CONST_DOUBLE_REAL_VALUE (op); + long real_words[VECTOR_128BIT_WORDS]; + + /* Make sure we don't overflow the real_words array and that it is + filled completely. */ + gcc_assert (num_words <= VECTOR_128BIT_WORDS && (bitsize % 32) == 0); + + real_to_target (real_words, rtype, mode); + + /* Iterate over each 32-bit word in the floating point constant. The + real_to_target function puts out words in target endian fashion. We need + to arrange the order so that the bytes are written in big endian order. */ + for (unsigned num = 0; num < num_words; num++) + { + unsigned endian_num = (BYTES_BIG_ENDIAN + ? num + : num_words - 1 - num); + + unsigned uvalue = real_words[endian_num]; + for (int shift = 32 - 8; shift >= 0; shift -= 8) + info->bytes[byte_num++] = (uvalue >> shift) & 0xff; + } + + /* Mark that this constant involves floating point. */ + info->fp_constant_p = true; +} + +/* Convert a vector constant OP with mode MODE to a vector 128-bit constant + structure INFO. + + Break out the constant out to bytes, half words, words, and double words. + Return true if we have successfully converted the constant. + + We handle CONST_INT, CONST_DOUBLE, CONST_VECTOR, and VEC_DUPLICATE of + constants. Integer and floating point scalar constants are splatted to fill + out the vector. */ + +bool +vec_const_128bit_to_bytes (rtx op, + machine_mode mode, + vec_const_128bit_type *info) +{ + /* Initialize the constant structure. */ + memset ((void *)info, 0, sizeof (vec_const_128bit_type)); + + /* Assume CONST_INTs are DImode. */ + if (mode == VOIDmode) + mode = CONST_INT_P (op) ? DImode : GET_MODE (op); + + if (mode == VOIDmode) + return false; + + unsigned size = GET_MODE_SIZE (mode); + bool splat_p = false; + + if (size > VECTOR_128BIT_BYTES) + return false; + + /* Set up the bits. */ + switch (GET_CODE (op)) + { + /* Integer constants, default to double word. */ + case CONST_INT: + { + constant_int_to_128bit_vector (op, mode, 0, info); + splat_p = true; + break; + } + + /* Floating point constants. */ + case CONST_DOUBLE: + { + /* Fail if the floating point constant is the wrong mode. */ + if (GET_MODE (op) != mode) + return false; + + /* SFmode stored as scalars are stored in DFmode format. */ + if (mode == SFmode) + { + mode = DFmode; + size = GET_MODE_SIZE (DFmode); + } + + constant_fp_to_128bit_vector (op, mode, 0, info); + splat_p = true; + break; + } + + /* Vector constants, iterate over each element. On little endian + systems, we have to reverse the element numbers. */ + case CONST_VECTOR: + { + /* Fail if the vector constant is the wrong mode or size. */ + if (GET_MODE (op) != mode + || GET_MODE_SIZE (mode) != VECTOR_128BIT_BYTES) + return false; + + machine_mode ele_mode = GET_MODE_INNER (mode); + size_t ele_size = GET_MODE_SIZE (ele_mode); + size_t nunits = GET_MODE_NUNITS (mode); + + for (size_t num = 0; num < nunits; num++) + { + rtx ele = CONST_VECTOR_ELT (op, num); + size_t byte_num = (BYTES_BIG_ENDIAN + ? num + : nunits - 1 - num) * ele_size; + + if (CONST_INT_P (ele)) + constant_int_to_128bit_vector (ele, ele_mode, byte_num, info); + else if (CONST_DOUBLE_P (ele)) + constant_fp_to_128bit_vector (ele, ele_mode, byte_num, info); + else + return false; + } + + break; + } + + /* Treat VEC_DUPLICATE of a constant just like a vector constant. + Since we are duplicating the element, we don't have to worry about + endian issues. */ + case VEC_DUPLICATE: + { + /* Fail if the vector duplicate is the wrong mode or size. */ + if (GET_MODE (op) != mode + || GET_MODE_SIZE (mode) != VECTOR_128BIT_BYTES) + return false; + + machine_mode ele_mode = GET_MODE_INNER (mode); + size_t ele_size = GET_MODE_SIZE (ele_mode); + rtx ele = XEXP (op, 0); + size_t nunits = GET_MODE_NUNITS (mode); + + if (!CONST_INT_P (ele) && !CONST_DOUBLE_P (ele)) + return false; + + for (size_t num = 0; num < nunits; num++) + { + size_t byte_num = num * ele_size; + + if (CONST_INT_P (ele)) + constant_int_to_128bit_vector (ele, ele_mode, byte_num, info); + else + constant_fp_to_128bit_vector (ele, ele_mode, byte_num, info); + } + + break; + } + + /* Any thing else, just return failure. */ + default: + return false; + } + + /* Splat the constant to fill 128 bits if desired. */ + if (splat_p && size < VECTOR_128BIT_BYTES) + { + if ((VECTOR_128BIT_BYTES % size) != 0) + return false; + + for (size_t offset = size; + offset < VECTOR_128BIT_BYTES; + offset += size) + memcpy ((void *) &info->bytes[offset], + (void *) &info->bytes[0], + size); + } + + /* Remember original size. */ + info->original_size = size; + + /* Determine if the bytes are all the same. */ + unsigned char first_byte = info->bytes[0]; + info->all_bytes_same = true; + for (size_t i = 1; i < VECTOR_128BIT_BYTES; i++) + if (first_byte != info->bytes[i]) + { + info->all_bytes_same = false; + break; + } + + /* Pack half words together & determine if all of the half words are the + same. */ + for (size_t i = 0; i < VECTOR_128BIT_HALF_WORDS; i++) + info->half_words[i] = ((info->bytes[i * 2] << 8) + | info->bytes[(i * 2) + 1]); + + unsigned short first_hword = info->half_words[0]; + info->all_half_words_same = true; + for (size_t i = 1; i < VECTOR_128BIT_HALF_WORDS; i++) + if (first_hword != info->half_words[i]) + { + info->all_half_words_same = false; + break; + } + + /* Pack words together & determine if all of the words are the same. */ + for (size_t i = 0; i < VECTOR_128BIT_WORDS; i++) + info->words[i] = ((info->bytes[i * 4] << 24) + | (info->bytes[(i * 4) + 1] << 16) + | (info->bytes[(i * 4) + 2] << 8) + | info->bytes[(i * 4) + 3]); + + info->all_words_same + = (info->words[0] == info->words[1] + && info->words[0] == info->words[1] + && info->words[0] == info->words[2] + && info->words[0] == info->words[3]); + + /* Pack double words together & determine if all of the double words are the + same. */ + for (size_t i = 0; i < VECTOR_128BIT_DOUBLE_WORDS; i++) + { + unsigned HOST_WIDE_INT d_word = 0; + for (size_t j = 0; j < 8; j++) + d_word = (d_word << 8) | info->bytes[(i * 8) + j]; + + info->double_words[i] = d_word; + } + + info->all_double_words_same + = (info->double_words[0] == info->double_words[1]); + + return true; +} + struct gcc_target targetm = TARGET_INITIALIZER; #include "gt-rs6000.h" >From jim.wilson.gcc@gmail.com Sat Dec 18 22:46:35 2021 Return-Path: X-Original-To: gcc-regression@gcc.gnu.org Delivered-To: gcc-regression@gcc.gnu.org Received: from mail-pj1-x102c.google.com (mail-pj1-x102c.google.com [IPv6:2607:f8b0:4864:20::102c]) by sourceware.org (Postfix) with ESMTPS id CA8433858433 for ; Sat, 18 Dec 2021 22:46:33 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.1 sourceware.org CA8433858433 Received: by mail-pj1-x102c.google.com with SMTP id b1-20020a17090a990100b001b14bd47532so5846516pjp.0 for ; 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([2601:646:c180:b150:2c6c:e374:ee58:ae10]) by smtp.gmail.com with ESMTPSA id z2sm13901043pff.107.2021.12.18.14.46.32 (version=TLS1_3 cipher=TLS_AES_128_GCM_SHA256 bits8/128); Sat, 18 Dec 2021 14:46:32 -0800 (PST) From: Jim Wilson X-Google-Original-From: Jim Wilson Message-ID: <6f6e31bc-7a49-bc70-acd8-f5d403c81a73@gmail.com> Date: Sat, 18 Dec 2021 14:45:49 -0800 MIME-Version: 1.0 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:91.0) Gecko/20100101 Thunderbird/91.3.1 Subject: Re: [TCWG CI] Regression caused by binutils: RISC-V: Added ld testcases for the medlow and medany code models. Content-Language: en-US To: ci_notify@linaro.org, Nelson Chu Cc: gcc-regression@gcc.gnu.org References: <1987826988.5741.1639818972031@jenkins.jenkins> In-Reply-To: <1987826988.5741.1639818972031@jenkins.jenkins> Content-Type: text/plain; charset=UTF-8; format=flowed Content-Transfer-Encoding: 7bit X-Spam-Status: No, score=-3.8 required=5.0 testsºYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, NICE_REPLY_A, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP autolearn=ham autolearn_force=no version=3.4.4 X-Spam-Checker-Version: SpamAssassin 3.4.4 (2020-01-24) on server2.sourceware.org X-BeenThere: gcc-regression@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc-regression mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 18 Dec 2021 22:46:35 -0000 On 12/18/21 01:16, ci_notify--- via Gcc-regression wrote: > [TCWG CI] Regression caused by binutils: RISC-V: Added ld testcases for the medlow and medany code models.: > commit fdb2b35b8fdbd5a6c136db326c73582dbfb335f8 > Author: Nelson Chu > > RISC-V: Added ld testcases for the medlow and medany code models. This doesn't make any sense. How does adding a RISC-V specific linker testcase break ARM builds? Even worse, I can find no useful info in the logs about what actually broke. It appears that your testing scripts are broken. Please disable your regression testing until you fix your scripts. Or at least modify them so that they don't bother innocent people with false and misleading bug reports. Jim