From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: from mail-wr1-x431.google.com (mail-wr1-x431.google.com [IPv6:2a00:1450:4864:20::431]) by sourceware.org (Postfix) with ESMTPS id A000A3858C3A for ; Thu, 7 Sep 2023 13:38:28 +0000 (GMT) DMARC-Filter: OpenDMARC Filter v1.4.2 sourceware.org A000A3858C3A Authentication-Results: sourceware.org; dmarc=none (p=none dis=none) header.from=embecosm.com Authentication-Results: sourceware.org; spf=pass smtp.mailfrom=embecosm.com Received: by mail-wr1-x431.google.com with SMTP id ffacd0b85a97d-31ad9155414so899863f8f.3 for ; Thu, 07 Sep 2023 06:38:28 -0700 (PDT) DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=embecosm.com; s=google; t=1694093907; x=1694698707; darn=gcc.gnu.org; h=content-transfer-encoding:mime-version:reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:from:to:cc:subject :date:message-id:reply-to; bh=e70MoCq7qUHP1GHQpBdTh5qXfWgp4wGIIStEmlDRbWo=; b=TNnY3r3gAIE9r4RHa98wLzWG7anhVE9qaYslCZYqWdsactdNonPYTouJd9OwnKr2sF 9jKpeLFbPxaLa2FaZw47569rZvFJlgLbRtzjk0ACJyghy6KkjqZUz2v6nhxLNXOMTvKL w48rV9MoJIOqth8Qg9C6yFLdRLxDna+k6gX4BFtBYvAcx3dK1cvP14Fh8NtwP0R9PqlL n2OzwDoxagNXLitLvV9HRxTstEWkapJ6NViaLwbiCXLpW/vs0fKW1uFXnXHg5ThkhZmx crgKj6ViGpTRVElXmT8gLrAzjLxl548b4LJMcf/0FeEPtKIG3Do9nTXzHEjBR4QABoTU RU4g== X-Google-DKIM-Signature: v=1; a=rsa-sha256; c=relaxed/relaxed; d=1e100.net; s=20221208; t=1694093907; x=1694698707; h=content-transfer-encoding:mime-version:reply-to:references :in-reply-to:message-id:date:subject:cc:to:from:x-gm-message-state :from:to:cc:subject:date:message-id:reply-to; bh=e70MoCq7qUHP1GHQpBdTh5qXfWgp4wGIIStEmlDRbWo=; b=YSi5N3tb/B+Htcw2G674KApTVq6/LRqwJ4snY3/LYC1F345xsGJ/UL62bY8RddNWoY 2b+Yxv+fHuh1Rv+17UX8IqeAXFNIdjwJQ6FHvIc9jwhYQGS9rDgZR+5mLNuvc6MBoiUh A3zE98h+/53YpmIgxBKL2NiLo6NgnL8AKrKBj1Iitn6SMWEx25bFS6iRRZh8Uil9YOwv q/k5MvcMXgS4gVjVhLR8ggmUf0fPpTAsVni4wcB/EB0+cJVUIimBoN+9ZG0D3TD1UkYq kLXsXtKfqSDp7AaMwM4Bjshi3KwtCTaXeHQTQuoz1s+gHmxYEV1iaKx7P5OQnZ1E4gr1 n9LQ== X-Gm-Message-State: AOJu0YwtJhW1oyiY5j1VX+TGpajNLIjAKx7Kc21+wVaF5oTqM3v9fZE/ zTYz41NTAthgNg1dNaaKgnUh X-Google-Smtp-Source: AGHT+IGc4tWWvDgS6xHb8g4bX5kzhrVBj8V2S6v3qZZafMH97onk7BbVWIQWT6bQ/8p+s12qCj4+hQ== X-Received: by 2002:adf:f149:0:b0:313:e456:e64a with SMTP id y9-20020adff149000000b00313e456e64amr4487327wro.21.1694093907425; Thu, 07 Sep 2023 06:38:27 -0700 (PDT) Received: from platypus.localdomain ([62.23.166.218]) by smtp.gmail.com with ESMTPSA id bt12-20020a056000080c00b0031433443265sm17693052wrb.53.2023.09.07.06.38.27 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Thu, 07 Sep 2023 06:38:27 -0700 (PDT) From: arthur.cohen@embecosm.com To: gcc-patches@gcc.gnu.org Cc: gcc-rust@gcc.gnu.org, ibuclaw@gdcproject.org Subject: [PATCH 04/14] rust: Implement TARGET_RUST_CPU_INFO for i[34567]86-*-* and x86_64-*-* Date: Thu, 7 Sep 2023 15:36:30 +0200 Message-ID: <20230907133729.2518969-5-arthur.cohen@embecosm.com> X-Mailer: git-send-email 2.42.0 In-Reply-To: <20230907133729.2518969-2-arthur.cohen@embecosm.com> References: <20230907133729.2518969-2-arthur.cohen@embecosm.com> Reply-To: arthur.cohen@embecosm.com MIME-Version: 1.0 Content-Transfer-Encoding: 8bit X-Spam-Status: No, score=-14.4 required=5.0 tests=BAYES_00,DKIM_SIGNED,DKIM_VALID,DKIM_VALID_AU,DKIM_VALID_EF,GIT_PATCH_0,KAM_SHORT,RCVD_IN_DNSWL_NONE,SPF_HELO_NONE,SPF_PASS,TXREP autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org List-Id: From: Iain Buclaw There are still quite a lot of the previously reverted i386-rust.cc missing, so it's only a partial reimplementation. gcc/ChangeLog: * config/i386/t-i386 (i386-rust.o): New rule. * config/i386/i386-rust.cc: New file. * config/i386/i386-rust.h: New file. --- gcc/config/i386/i386-rust.cc | 129 +++++++++++++++++++++++++++++++++++ gcc/config/i386/i386-rust.h | 22 ++++++ gcc/config/i386/t-i386 | 4 ++ 3 files changed, 155 insertions(+) create mode 100644 gcc/config/i386/i386-rust.cc create mode 100644 gcc/config/i386/i386-rust.h diff --git a/gcc/config/i386/i386-rust.cc b/gcc/config/i386/i386-rust.cc new file mode 100644 index 00000000000..a00c4f8cee1 --- /dev/null +++ b/gcc/config/i386/i386-rust.cc @@ -0,0 +1,129 @@ +/* Subroutines for the Rust front end on the x86 architecture. + Copyright (C) 2022 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +#define IN_TARGET_CODE 1 + +#include "config.h" +#include "system.h" +#include "coretypes.h" +#include "tm.h" +#include "tm_rust.h" +#include "rust/rust-target.h" + +/* Implement TARGET_RUST_CPU_INFO for x86 targets. */ + +void +ix86_rust_target_cpu_info (void) +{ + if (TARGET_64BIT) + rust_add_target_info ("target_arch", "x86_64"); + else + rust_add_target_info ("target_arch", "x86"); + + // features officially "stabilised" in rustc + if (TARGET_MMX) + rust_add_target_info ("target_feature", "mmx"); + if (TARGET_SSE) + rust_add_target_info ("target_feature", "sse"); + if (TARGET_SSE2) + rust_add_target_info ("target_feature", "sse2"); + if (TARGET_SSE3) + rust_add_target_info ("target_feature", "sse3"); + if (TARGET_SSSE3) + rust_add_target_info ("target_feature", "ssse3"); + if (TARGET_SSE4_1) + rust_add_target_info ("target_feature", "sse4.1"); + if (TARGET_SSE4_2) + rust_add_target_info ("target_feature", "sse4.2"); + if (TARGET_AES) + rust_add_target_info ("target_feature", "aes"); + if (TARGET_SHA) + rust_add_target_info ("target_feature", "sha"); + if (TARGET_AVX) + rust_add_target_info ("target_feature", "avx"); + if (TARGET_AVX2) + rust_add_target_info ("target_feature", "avx2"); + if (TARGET_AVX512F) + rust_add_target_info ("target_feature", "avx512f"); + if (TARGET_AVX512ER) + rust_add_target_info ("target_feature", "avx512er"); + if (TARGET_AVX512CD) + rust_add_target_info ("target_feature", "avx512cd"); + if (TARGET_AVX512PF) + rust_add_target_info ("target_feature", "avx512pf"); + if (TARGET_AVX512DQ) + rust_add_target_info ("target_feature", "avx512dq"); + if (TARGET_AVX512BW) + rust_add_target_info ("target_feature", "avx512bw"); + if (TARGET_AVX512VL) + rust_add_target_info ("target_feature", "avx512vl"); + if (TARGET_AVX512VBMI) + rust_add_target_info ("target_feature", "avx512vbmi"); + if (TARGET_AVX512IFMA) + rust_add_target_info ("target_feature", "avx512ifma"); + if (TARGET_AVX512VPOPCNTDQ) + rust_add_target_info ("target_feature", "avx512vpopcntdq"); + if (TARGET_FMA) + rust_add_target_info ("target_feature", "fma"); + if (TARGET_RTM) + rust_add_target_info ("target_feature", "rtm"); + if (TARGET_SSE4A) + rust_add_target_info ("target_feature", "sse4a"); + if (TARGET_BMI) + { + rust_add_target_info ("target_feature", "bmi1"); + rust_add_target_info ("target_feature", "bmi"); + } + if (TARGET_BMI2) + rust_add_target_info ("target_feature", "bmi2"); + if (TARGET_LZCNT) + rust_add_target_info ("target_feature", "lzcnt"); + if (TARGET_TBM) + rust_add_target_info ("target_feature", "tbm"); + if (TARGET_POPCNT) + rust_add_target_info ("target_feature", "popcnt"); + if (TARGET_RDRND) + { + rust_add_target_info ("target_feature", "rdrand"); + rust_add_target_info ("target_feature", "rdrnd"); + } + if (TARGET_F16C) + rust_add_target_info ("target_feature", "f16c"); + if (TARGET_RDSEED) + rust_add_target_info ("target_feature", "rdseed"); + if (TARGET_ADX) + rust_add_target_info ("target_feature", "adx"); + if (TARGET_FXSR) + rust_add_target_info ("target_feature", "fxsr"); + if (TARGET_XSAVE) + rust_add_target_info ("target_feature", "xsave"); + if (TARGET_XSAVEOPT) + rust_add_target_info ("target_feature", "xsaveopt"); + if (TARGET_XSAVEC) + rust_add_target_info ("target_feature", "xsavec"); + if (TARGET_XSAVES) + rust_add_target_info ("target_feature", "xsaves"); + if (TARGET_VPCLMULQDQ) + { + rust_add_target_info ("target_feature", "pclmulqdq"); + rust_add_target_info ("target_feature", "vpclmulqdq"); + } + if (TARGET_CMPXCHG16B) + rust_add_target_info ("target_feature", "cmpxchg16b"); + if (TARGET_MOVBE) + rust_add_target_info ("target_feature", "movbe"); +} diff --git a/gcc/config/i386/i386-rust.h b/gcc/config/i386/i386-rust.h new file mode 100644 index 00000000000..a837e2f1c74 --- /dev/null +++ b/gcc/config/i386/i386-rust.h @@ -0,0 +1,22 @@ +/* Definitions for the Rust front end on the x86 architecture. + Copyright (C) 2022 Free Software Foundation, Inc. + +GCC is free software; you can redistribute it and/or modify +it under the terms of the GNU General Public License as published by +the Free Software Foundation; either version 3, or (at your option) +any later version. + +GCC is distributed in the hope that it will be useful, +but WITHOUT ANY WARRANTY; without even the implied warranty of +MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +GNU General Public License for more details. + +You should have received a copy of the GNU General Public License +along with GCC; see the file COPYING3. If not see +. */ + +/* In i386-rust.cc */ +extern void ix86_rust_target_cpu_info (void); + +/* Target CPU info for Rust. */ +#define TARGET_RUST_CPU_INFO ix86_rust_target_cpu_info diff --git a/gcc/config/i386/t-i386 b/gcc/config/i386/t-i386 index b417c7f17ec..f85817d698c 100644 --- a/gcc/config/i386/t-i386 +++ b/gcc/config/i386/t-i386 @@ -46,6 +46,10 @@ i386-d.o: $(srcdir)/config/i386/i386-d.cc $(COMPILE) $< $(POSTCOMPILE) +i386-rust.o: $(srcdir)/config/i386/i386-rust.cc + $(COMPILE) $< + $(POSTCOMPILE) + i386-options.o: $(srcdir)/config/i386/i386-options.cc $(COMPILE) $< $(POSTCOMPILE) -- 2.42.0