From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8097 invoked by alias); 27 Dec 2002 12:02:28 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 8088 invoked from network); 27 Dec 2002 12:02:27 -0000 Received: from unknown (HELO smtp3.libero.it) (193.70.192.127) by sources.redhat.com with SMTP; 27 Dec 2002 12:02:27 -0000 Received: from engineer (151.24.17.236) by smtp3.libero.it (6.7.015) id 3E08AEE4001586C4; Fri, 27 Dec 2002 13:02:27 +0100 Message-ID: <000701c2ad9e$a85adbc0$ec111897@bonz> From: "Bonzini" To: Cc: Subject: Re: An unusual Performance approach using Synthetic registers, and a request for guidance. Date: Fri, 27 Dec 2002 06:48:00 -0000 MIME-Version: 1.0 Content-Type: text/plain; charset="iso-8859-1" Content-Transfer-Encoding: 7bit X-Priority: 3 X-MSMail-Priority: Normal X-MimeOLE: Produced By Microsoft MimeOLE V5.00.2919.6700 X-SW-Source: 2002-12/txt/msg01447.txt.bz2 That's not unusual. If one had, say, to write a back-end for the 6502, one might think of representing the zero-page as caller-save registers, and hide the weeny three registers A,X,Y from the middle-end (using them only internally, or very near to this). I also hope that because of the good L1 coherency of the stack, this might pay well on the x86 as well. The only problem might be in the lack of orthogonality in the x86 instruction set. Go ahead, and good luck! Paolo