Re: -msse producing sse2 instructions

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

----- Original Message -----
From: "Mark Hahn" <hahn@physics.mcmaster.ca>
To: "Dylan Cuthbert" <dylan@q-games.com>
Sent: Monday, July 22, 2002 3:10 AM
Subject: Re: -msse producing sse2 instructions


>
> but are you sure the software on the two machines is otherwise
> *identical*?  for instance, libc, ld.so, kernel, etc?  they all
> can potentially affect alignment.  if not, the comparison certainly does
not
> point to a cpu difference.
>

They are both (the Athlon MP and the Athlon 4) a pretty much vanilla install
of the latest cygwin environment.

There are two Athlon 4 machines (each with the latest cygwin environment)
and both exhibit the same problem.

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

Re: -msse producing sse2 instructions

[Ross Smith]

On Tuesday, 23 July 2002 14:00, Dylan Cuthbert wrote:
> Sorry, my mistake, my eye read what I wanted to see, the Athlon-XP
> finally has *full* unequivocal support for SSE.  no SSE2.  I presume
> the Athlon-MP and Athlon-4 Mobile still have a few problems in their
> SSE implementation?

No, the XP, MP, and Mobile 4 all use the same core (Model 6 = Palomino, 
or Model 7 = Thoroughbred in some of the recent ones), and all support 
the same instruction set.

-- 
Ross Smith ..................................... Auckland, New Zealand
r-smith@ihug.co.nz ...................................................

        "A specter is haunting Wall Street; it is the specter
        of honest accounting."           -- Arthur D. Hlavaty

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

Sorry, my mistake, my eye read what I wanted to see, the Athlon-XP finally
has *full* unequivocal support for SSE.  no SSE2.  I presume the Athlon-MP
and Athlon-4 Mobile still have a few problems in their SSE implementation?

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Guillermo Ballester Valor" <gbv@oxixares.com>
Cc: <gcc@gcc.gnu.org>
Sent: Tuesday, July 23, 2002 6:08 AM
Subject: Re: -msse producing sse2 instructions


> Guillermo Ballester Valor <gbv@oxixares.com> writes:
>
> > Hi,
> >
> > On Monday 22 July 2002 11:44, Dylan Cuthbert wrote:
> >
> >> The Athlon-XP  fully supports SSE2.
> >
> > This is a big surprise to me. I always thought Hammer would be the first
AMD
> > processor with SSE2 extensions support. And I am the owner of an Athlon
XP :)
>
> You're right.  Hammers are the first SSE2 capable AMD processors,
>
> Andreas
> --
>  Andreas Jaeger
>   SuSE Labs aj@suse.de
>    private aj@arthur.inka.de
>     http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Andreas Jaeger]

Guillermo Ballester Valor <gbv@oxixares.com> writes:

> Hi,
>
> On Monday 22 July 2002 11:44, Dylan Cuthbert wrote:
>
>> The Athlon-XP  fully supports SSE2.
>
> This is a big surprise to me. I always thought Hammer would be the first AMD 
> processor with SSE2 extensions support. And I am the owner of an Athlon XP :)

You're right.  Hammers are the first SSE2 capable AMD processors,

Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Guillermo Ballester Valor]

Hi,

On Monday 22 July 2002 11:44, Dylan Cuthbert wrote:

> The Athlon-XP  fully supports SSE2.

This is a big surprise to me. I always thought Hammer would be the first AMD 
processor with SSE2 extensions support. And I am the owner of an Athlon XP :)

Guillermo.

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

Ross has found the problem.

After rummaging around in the Athlon XP docs, I found out the following:

The Athlon-4 Thunderbird only supports a subset of SSE instructions and
reports no SSE extensions when running cpuid.

The Athlon-MP and the Athlon-4 Mobile supports the full SSE set but not
SSE2.
The Athlon-XP  fully supports SSE2.

So it isn't a gcc problem *and* it is a gcc problem, the compiler is ok, but
the "athlon-4" usage throughout the gcc docs is a misnomer and confusing,
and also AMD should use better naming conventions! :-)

Regards
---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

----- Original Message -----
From: "Ross Smith" <r-smith@ihug.co.nz>
To: "Dylan Cuthbert" <dylan@q-games.com>; "Andreas Jaeger" <aj@suse.de>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
Sent: Monday, July 22, 2002 3:55 PM
Subject: Re: -msse producing sse2 instructions


> On Monday, 22 July 2002 02:57, Dylan Cuthbert wrote:
> > Hello there,
> >
> > Well, I run the same executable on an Athlon MP with no problem.
> > When I run on an Athlon 4 gdb tells me the program has crashed with
> > an illegal instruction and displays that instruction I sent earlier.
>
> Is the other system an Athlon Model 4 (a.k.a. Thunderbird) or a Mobile
> Athlon 4 (a.k.a. Mobile Athlon Model 6)? They're not the same chip. The
> former doesn't support SSE, the latter does.
>
> Most people use "Athlon 4" to mean Athlon Model 4, but GCC aids AMD in
> confusing the issue by using "athlon-4" in the architecture options to
> refer to the Mobile Athlon 4.
>
> --
> Ross Smith ..................................... Auckland, New Zealand
> r-smith@ihug.co.nz ...................................................
>
>         "A specter is haunting Wall Street; it is the specter
>         of honest accounting."           -- Arthur D. Hlavaty
>

Re: -msse producing sse2 instructions

[Ross Smith]

On Monday, 22 July 2002 02:57, Dylan Cuthbert wrote:
> Hello there,
>
> Well, I run the same executable on an Athlon MP with no problem. 
> When I run on an Athlon 4 gdb tells me the program has crashed with
> an illegal instruction and displays that instruction I sent earlier.

Is the other system an Athlon Model 4 (a.k.a. Thunderbird) or a Mobile 
Athlon 4 (a.k.a. Mobile Athlon Model 6)? They're not the same chip. The 
former doesn't support SSE, the latter does.

Most people use "Athlon 4" to mean Athlon Model 4, but GCC aids AMD in 
confusing the issue by using "athlon-4" in the architecture options to 
refer to the Mobile Athlon 4.

-- 
Ross Smith ..................................... Auckland, New Zealand
r-smith@ihug.co.nz ...................................................

        "A specter is haunting Wall Street; it is the specter
        of honest accounting."           -- Arthur D. Hlavaty

Re: -msse producing sse2 instructions

[Andreas Jaeger]

"Dylan Cuthbert" <dylan@q-games.com> writes:

> Hi all,
>
> I managed to whittle it down to the place where the instruction is being
> generated.. and the resulting executable produces an Illegal Instruction if
> run on Athlon 4 machines, but not on Athlon MP/XP or Pentium 4s.
>
> The line to compile with:
>
> $>
> g++ -mcpu=pentium3 -march=pentium3 -msse -mfpmath=387 -mpreferred-stack-boun
> dary=4 -fno-implement-inlines -Werror -Wall  -Dstdext=__gnu_cxx -O2 -mno-cyg
> win -mwin32  test.cpp -o test.exe
>
> Compiling with -march=athlon-4 -mcpu=athlon-4 also causes the same code to
> be generated.
>
> On another note, I also get an illegal instruction error on this:
>
> movss  0xfffffffc(%ebp),%xmm0
>
> Seems to be in the integer->float conversion code tho. so I hope this helps.

I compiled your code and it worked fine on both my Pentium III and
Athlon MP.

The first Athlon4 systems had SSE disabled in the BIOS.  As Honza
already mentioned, you should use the cpuid instruction and check
whether your systems support SSE at all.

For example my Athlon4 reports these flags via cpuinfo (this is read
from a Linux file):
flags           : fpu vme de pse tsc msr pae mce cx8 apic sep mtrr pge mca cmov pat pse36 mmx fxsr sse syscall mmxext 3dnowext 3dnow

Please write some assembler and check whether the Athlons do support
SSE and if not, investigate why not.

I do not think that this is a GCC problem,
Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

[-- Attachment #1: Type: text/plain, Size: 1864 bytes --]

Hi all,

I managed to whittle it down to the place where the instruction is being
generated.. and the resulting executable produces an Illegal Instruction if
run on Athlon 4 machines, but not on Athlon MP/XP or Pentium 4s.

The line to compile with:

$>
g++ -mcpu=pentium3 -march=pentium3 -msse -mfpmath=387 -mpreferred-stack-boun
dary=4 -fno-implement-inlines -Werror -Wall  -Dstdext=__gnu_cxx -O2 -mno-cyg
win -mwin32  test.cpp -o test.exe

Compiling with -march=athlon-4 -mcpu=athlon-4 also causes the same code to
be generated.

On another note, I also get an illegal instruction error on this:

movss  0xfffffffc(%ebp),%xmm0

Seems to be in the integer->float conversion code tho. so I hope this helps.

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com



----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Dylan Cuthbert" <dylan@q-games.com>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
Sent: Monday, July 22, 2002 1:43 AM
Subject: Re: -msse producing sse2 instructions


> "Dylan Cuthbert" <dylan@q-games.com> writes:
>
> > Hello there,
> >
> > Well, I run the same executable on an Athlon MP with no problem.  When I
run
> > on an Athlon 4 gdb tells me the program has crashed with an illegal
> > instruction and displays that instruction I sent earlier.
> >
> > However, as Tim Prince mentioned, it might be an alignment issue with
> > different versions of the Athlon being more fussy about alignment than
> > others and invalidly reporting the problem as an illegal instruction.
>
> Not necessarily different versions of an Athlon, but different
> environments.
>
> But without an example programs we cannot do any further investigation
> and any discussion is mood.
>
> Andreas
> --
>  Andreas Jaeger
>   SuSE Labs aj@suse.de
>    private aj@arthur.inka.de
>     http://www.suse.de/~aj

[-- Attachment #2: test.tgz --]
[-- Type: application/x-compressed, Size: 92784 bytes --]

Re: -msse producing sse2 instructions

[Christopher Faylor]

On Sun, Jul 21, 2002 at 07:21:43AM -0700, Tim Prince wrote:
>I think Chris Faylor decided to stay with 4-byte alignment for
>backwards compatibility with the libstdc++-v2 libraries.

AFAICT, it was the alignment of the .ctor section that was causing the
problem.  I think I have patched the gcc-2.95.3 binaries to work
correctly now, so once I've officially released gcc 3.2 and
gcc2-2.95.3-9, I will also be able to eventually release a version of
binutils with a greater alignment.

cgf

Re: -msse producing sse2 instructions

[Gareth Pearce]

>
>"Gareth Pearce" <tilps@hotmail.com> writes:
>
> > ----- Original Message -----
> > From: "Andreas Jaeger" <aj@suse.de>
> > To: "Dylan Cuthbert" <dylan@q-games.com>
> > Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
> > Sent: Sunday, July 21, 2002 11:28 PM
> > Subject: Re: -msse producing sse2 instructions
> >
> >
> >> "Dylan Cuthbert" <dylan@q-games.com> writes:
> >>
> >> > Hello there, thanks for the quick response.
> >> >
> >> > Whilst I see if I can track down a small test program (it only occurs 
>in
> > the
> >> > big unwieldy programs right now, as these things always seem to do)
> > here's
> >> > some extra info:
> >> >
> >> > I'm compiling currently
> >> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 
>3.1.1-4
> > from
> >> > the very latest experimental cygwin distribution.
> >>
> >>
> >> > One of the problems with tracking this down is my machine is an 
>Athlon
> > MP
> >> > and has no trouble with SSE2 instructions, however a client's machine 
>is
> > an
> >> > Athlon 4 and exhibits the problem.  And of course we need the SSE
> > builtins
> >> > for speed improvements. -_-;;
> >>
> >> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> >> SSE only).
> >>
> >> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> >> Therefore are you sure that you get an Illegal instruction for
> >> cvttss2si?  Or is this some other error and you're just confused.
> >
> > please ignore me if i am showing my ignorance ... but I have in the past
> > recieved the impression that athlon SSE implementation is not completely
> > compatible with intel SSE, and under some circumstances will result in
> > illegal instructions. (different athlon revisions have better/worse
> > support).
>
>It should be compatible - if not, report it, so that we can verify it
>and change GCC so that using SSE on Athlon 4s will do the right thing.

I believe the situation described as having a patch waiting for it in the 
other fork of this thread sounds very similar to past experience, and is 
quite probably what I was thinking of.

Gareth


_________________________________________________________________
MSN Photos is the easiest way to share and print your photos: 
http://photos.msn.com/support/worldwide.aspx

Re: -msse producing sse2 instructions

[Tim Prince]

On Sunday 21 July 2002 11:44, Jan Hubicka wrote:
> > Hello there,
> >
> > Well, I run the same executable on an Athlon MP with no problem.  When I
> > run on an Athlon 4 gdb tells me the program has crashed with an illegal
> > instruction and displays that instruction I sent earlier.
> >
> > However, as Tim Prince mentioned, it might be an alignment issue with
> > different versions of the Athlon being more fussy about alignment than
> > others and invalidly reporting the problem as an illegal instruction.
>
> This does not happen.  The missaligned accesses are reported as
> segmentation violation and additionally the instruction is scalar and
> does not require any alignment.  I would bet to the BIOS or Windows
> problem.  It is possible to verify whether SSE is enabled by cpuid
> instruction that is available in Linux systems in /proc/cpuinfo but I am
> not sure whether there is some equivalent for W.
>
> Honza
Honza is correct; any problem with alignment would be distinct 
from whether your CPU accepts sse instructions.  Perhaps that is an older 
version of Athlon.

The cpuid instructions work the same with gcc under Windows, and, with the 
necessary syntax changes, with other compilers.  Certain applications, such 
as those built with the Intel compiler option /QaxK, do use cpuid to 
determine whether sse instructions are available.  Information obtained by 
cpuid may be distinct from the information available in /proc/cpuinfo, 
although some of the latter would express results of cpuid tests.
-- 
Tim Prince

Re: -msse producing sse2 instructions

[Tim Prince]

On Sunday 21 July 2002 11:42, Jan Hubicka wrote:
> 
> > -march=pentium3 doesn't set x86_partial_reg_dependency as =athlon and
> > =pentium4 do.  This is the flag which tells gcc to use movaps for
> > register to register moves.  This sometimes causes sse code to be slower
> > than 387 code. If it were not for this problem, -march=pentium3 would be
> > a good common denominator for P3/P4/AthlonMP.
>
> I have patch for this problem.  I will commit it soon.
>
Thanks.

-- 
Tim Prince

Re: -msse producing sse2 instructions

[Jan Hubicka]

> 
> Hello there,
> 
> Well, I run the same executable on an Athlon MP with no problem.  When I run
> on an Athlon 4 gdb tells me the program has crashed with an illegal
> instruction and displays that instruction I sent earlier.
> 
> However, as Tim Prince mentioned, it might be an alignment issue with
> different versions of the Athlon being more fussy about alignment than
> others and invalidly reporting the problem as an illegal instruction.

This does not happen.  The missaligned accesses are reported as
segmentation violation and additionally the instruction is scalar and
does not require any alignment.  I would bet to the BIOS or Windows
problem.  It is possible to verify whether SSE is enabled by cpuid
instruction that is available in Linux systems in /proc/cpuinfo but I am
not sure whether there is some equivalent for W.

Honza
> 
> Regards
> 
> ---------------------------------
> Q-Games, Dylan Cuthbert.
> http://www.q-games.com
> 
> ----- Original Message -----
> From: "Andreas Jaeger" <aj@suse.de>
> To: "Dylan Cuthbert" <dylan@q-games.com>
> Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
> Sent: Sunday, July 21, 2002 10:28 PM
> Subject: Re: -msse producing sse2 instructions
> 
> 
> > "Dylan Cuthbert" <dylan@q-games.com> writes:
> >
> > > Hello there, thanks for the quick response.
> > >
> > > Whilst I see if I can track down a small test program (it only occurs in
> the
> > > big unwieldy programs right now, as these things always seem to do)
> here's
> > > some extra info:
> > >
> > > I'm compiling currently
> > > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> from
> > > the very latest experimental cygwin distribution.
> >
> >
> > > One of the problems with tracking this down is my machine is an Athlon
> MP
> > > and has no trouble with SSE2 instructions, however a client's machine is
> an
> > > Athlon 4 and exhibits the problem.  And of course we need the SSE
> builtins
> > > for speed improvements. -_-;;
> >
> > Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> > SSE only).
> >
> > Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> > Therefore are you sure that you get an Illegal instruction for
> > cvttss2si?  Or is this some other error and you're just confused.
> >
> > Andreas
> > --
> >  Andreas Jaeger
> >   SuSE Labs aj@suse.de
> >    private aj@arthur.inka.de
> >     http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Jan Hubicka]

> On Sunday 21 July 2002 06:28, Andreas Jaeger wrote:
> > "Dylan Cuthbert" <dylan@q-games.com> writes:
> ....
> > > I'm compiling currently
> > > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> > > from the very latest experimental cygwin distribution.
> > >
> > >
> > > One of the problems with tracking this down is my machine is an Athlon MP
> > > and has no trouble with SSE2 instructions, however a client's machine is
> > > an Athlon 4 and exhibits the problem.  And of course we need the SSE
> > > builtins for speed improvements. -_-;;
> >
> > Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> > SSE only).
> >
> > Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> > Therefore are you sure that you get an Illegal instruction for
> > cvttss2si?  Or is this some other error and you're just confused.
> >
> > Andreas
> -march=pentium3 doesn't set x86_partial_reg_dependency as =athlon and 
> =pentium4 do.  This is the flag which tells gcc to use movaps for register to 
> register moves.  This sometimes causes sse code to be slower than 387 code.  
> If it were not for this problem, -march=pentium3 would be a good common 
> denominator for P3/P4/AthlonMP.
> 

I have patch for this problem.  I will commit it soon.

> The cvttss2si instructions are working fine on my old P-III's.

Perhaps the chip has SSE disabled by bios or the Windows you are using
is not SSE aware?

Honza
> 
> How are you dealing with alignment with your cygwin binutils?  You would not 
> be able to use sse parallel memory instructions without applying 16-byte 
> alignment.  At least, the odds are against them.  I think Chris Faylor 
> decided to stay with 4-byte alignment for backwards compatibility with the 
> libstdc++-v2 libraries.
> -- 
> Tim Prince

Re: -msse producing sse2 instructions

[Andreas Jaeger]

"Dylan Cuthbert" <dylan@q-games.com> writes:

> Hello there,
>
> Well, I run the same executable on an Athlon MP with no problem.  When I run
> on an Athlon 4 gdb tells me the program has crashed with an illegal
> instruction and displays that instruction I sent earlier.
>
> However, as Tim Prince mentioned, it might be an alignment issue with
> different versions of the Athlon being more fussy about alignment than
> others and invalidly reporting the problem as an illegal instruction.

Not necessarily different versions of an Athlon, but different
environments.

But without an example programs we cannot do any further investigation
and any discussion is mood.

Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

Hello there,

Well, I run the same executable on an Athlon MP with no problem.  When I run
on an Athlon 4 gdb tells me the program has crashed with an illegal
instruction and displays that instruction I sent earlier.

However, as Tim Prince mentioned, it might be an alignment issue with
different versions of the Athlon being more fussy about alignment than
others and invalidly reporting the problem as an illegal instruction.

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Dylan Cuthbert" <dylan@q-games.com>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
Sent: Sunday, July 21, 2002 10:28 PM
Subject: Re: -msse producing sse2 instructions


> "Dylan Cuthbert" <dylan@q-games.com> writes:
>
> > Hello there, thanks for the quick response.
> >
> > Whilst I see if I can track down a small test program (it only occurs in
the
> > big unwieldy programs right now, as these things always seem to do)
here's
> > some extra info:
> >
> > I'm compiling currently
> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
from
> > the very latest experimental cygwin distribution.
>
>
> > One of the problems with tracking this down is my machine is an Athlon
MP
> > and has no trouble with SSE2 instructions, however a client's machine is
an
> > Athlon 4 and exhibits the problem.  And of course we need the SSE
builtins
> > for speed improvements. -_-;;
>
> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> SSE only).
>
> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> Therefore are you sure that you get an Illegal instruction for
> cvttss2si?  Or is this some other error and you're just confused.
>
> Andreas
> --
>  Andreas Jaeger
>   SuSE Labs aj@suse.de
>    private aj@arthur.inka.de
>     http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Tim Prince]

On Sunday 21 July 2002 06:28, Andreas Jaeger wrote:
> "Dylan Cuthbert" <dylan@q-games.com> writes:
....
> > I'm compiling currently
> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> > from the very latest experimental cygwin distribution.
> >
> >
> > One of the problems with tracking this down is my machine is an Athlon MP
> > and has no trouble with SSE2 instructions, however a client's machine is
> > an Athlon 4 and exhibits the problem.  And of course we need the SSE
> > builtins for speed improvements. -_-;;
>
> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> SSE only).
>
> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> Therefore are you sure that you get an Illegal instruction for
> cvttss2si?  Or is this some other error and you're just confused.
>
> Andreas
-march=pentium3 doesn't set x86_partial_reg_dependency as =athlon and 
=pentium4 do.  This is the flag which tells gcc to use movaps for register to 
register moves.  This sometimes causes sse code to be slower than 387 code.  
If it were not for this problem, -march=pentium3 would be a good common 
denominator for P3/P4/AthlonMP.

The cvttss2si instructions are working fine on my old P-III's.

How are you dealing with alignment with your cygwin binutils?  You would not 
be able to use sse parallel memory instructions without applying 16-byte 
alignment.  At least, the odds are against them.  I think Chris Faylor 
decided to stay with 4-byte alignment for backwards compatibility with the 
libstdc++-v2 libraries.
-- 
Tim Prince

Re: -msse producing sse2 instructions

[Andreas Jaeger]

"Gareth Pearce" <tilps@hotmail.com> writes:

> ----- Original Message -----
> From: "Andreas Jaeger" <aj@suse.de>
> To: "Dylan Cuthbert" <dylan@q-games.com>
> Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
> Sent: Sunday, July 21, 2002 11:28 PM
> Subject: Re: -msse producing sse2 instructions
>
>
>> "Dylan Cuthbert" <dylan@q-games.com> writes:
>>
>> > Hello there, thanks for the quick response.
>> >
>> > Whilst I see if I can track down a small test program (it only occurs in
> the
>> > big unwieldy programs right now, as these things always seem to do)
> here's
>> > some extra info:
>> >
>> > I'm compiling currently
>> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
> from
>> > the very latest experimental cygwin distribution.
>>
>>
>> > One of the problems with tracking this down is my machine is an Athlon
> MP
>> > and has no trouble with SSE2 instructions, however a client's machine is
> an
>> > Athlon 4 and exhibits the problem.  And of course we need the SSE
> builtins
>> > for speed improvements. -_-;;
>>
>> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
>> SSE only).
>>
>> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
>> Therefore are you sure that you get an Illegal instruction for
>> cvttss2si?  Or is this some other error and you're just confused.
>
> please ignore me if i am showing my ignorance ... but I have in the past
> recieved the impression that athlon SSE implementation is not completely
> compatible with intel SSE, and under some circumstances will result in
> illegal instructions. (different athlon revisions have better/worse
> support).

It should be compatible - if not, report it, so that we can verify it
and change GCC so that using SSE on Athlon 4s will do the right thing.

Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Gareth Pearce]

----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Dylan Cuthbert" <dylan@q-games.com>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
Sent: Sunday, July 21, 2002 11:28 PM
Subject: Re: -msse producing sse2 instructions


> "Dylan Cuthbert" <dylan@q-games.com> writes:
>
> > Hello there, thanks for the quick response.
> >
> > Whilst I see if I can track down a small test program (it only occurs in
the
> > big unwieldy programs right now, as these things always seem to do)
here's
> > some extra info:
> >
> > I'm compiling currently
> > with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4
from
> > the very latest experimental cygwin distribution.
>
>
> > One of the problems with tracking this down is my machine is an Athlon
MP
> > and has no trouble with SSE2 instructions, however a client's machine is
an
> > Athlon 4 and exhibits the problem.  And of course we need the SSE
builtins
> > for speed improvements. -_-;;
>
> Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
> SSE only).
>
> Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
> Therefore are you sure that you get an Illegal instruction for
> cvttss2si?  Or is this some other error and you're just confused.

please ignore me if i am showing my ignorance ... but I have in the past
recieved the impression that athlon SSE implementation is not completely
compatible with intel SSE, and under some circumstances will result in
illegal instructions. (different athlon revisions have better/worse
support).


Gareth

Re: -msse producing sse2 instructions

[Andreas Jaeger]

"Dylan Cuthbert" <dylan@q-games.com> writes:

> Hello there, thanks for the quick response.
>
> Whilst I see if I can track down a small test program (it only occurs in the
> big unwieldy programs right now, as these things always seem to do) here's
> some extra info:
>
> I'm compiling currently
> with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4 from
> the very latest experimental cygwin distribution.


> One of the problems with tracking this down is my machine is an Athlon MP
> and has no trouble with SSE2 instructions, however a client's machine is an
> Athlon 4 and exhibits the problem.  And of course we need the SSE builtins
> for speed improvements. -_-;;

Athlon 4s do not have SSE2, they're the same as Athlon MP (both have
SSE only).

Btw. cvttss2si is an SSE instruction, not an SSE2 one AFAIK.
Therefore are you sure that you get an Illegal instruction for
cvttss2si?  Or is this some other error and you're just confused.

Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Dylan Cuthbert]

Hello there, thanks for the quick response.

Whilst I see if I can track down a small test program (it only occurs in the
big unwieldy programs right now, as these things always seem to do) here's
some extra info:

I'm compiling currently
with -mfpmath=387 -msse -mcpu=pentium3 -march=pentium3 and gcc 3.1.1-4 from
the very latest experimental cygwin distribution.

One of the problems with tracking this down is my machine is an Athlon MP
and has no trouble with SSE2 instructions, however a client's machine is an
Athlon 4 and exhibits the problem.  And of course we need the SSE builtins
for speed improvements. -_-;;

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com

----- Original Message -----
From: "Andreas Jaeger" <aj@suse.de>
To: "Dylan Cuthbert" <dylan@q-games.com>
Cc: <gcc@gcc.gnu.org>; "Jan Hubicka" <jh@suse.cz>
Sent: Sunday, July 21, 2002 9:08 PM
Subject: Re: -msse producing sse2 instructions


> "Dylan Cuthbert" <dylan@q-games.com> writes:
>
> > Hi there,
> >
> > I'm having problems compiling with the -msse option and cygwin's latest
gcc
> > (v3.1.1), it seems to be producing SSE2 instructions which my Athlon 4
is
> > faithfully reporting as illegal instructions.  The athlon 4 should
support
> > standard SSE but not SSE2 instructions.
> >
> > The current illegal instruction (one of a few others I've had but
forgotten
> > to record) is:
> >
> > cvttss2si 0xffffffd8(%ebp),%eax
> >
> > Removing the -msse option completely of course clears up the problem but
I
> > want to use the builtins and the 128 bit vector types available
with -msse.
> >
> > Is there any way as a temporary solution to disable sse code generation
but
> > still allow use of the builtins?
>
> Please file a complete bug report including a small test program that
> shows this behaviour,
>
> Andreas
> --
>  Andreas Jaeger
>   SuSE Labs aj@suse.de
>    private aj@arthur.inka.de
>     http://www.suse.de/~aj

Re: -msse producing sse2 instructions

[Andreas Jaeger]

"Dylan Cuthbert" <dylan@q-games.com> writes:

> Hi there,
>
> I'm having problems compiling with the -msse option and cygwin's latest gcc
> (v3.1.1), it seems to be producing SSE2 instructions which my Athlon 4 is
> faithfully reporting as illegal instructions.  The athlon 4 should support
> standard SSE but not SSE2 instructions.
>
> The current illegal instruction (one of a few others I've had but forgotten
> to record) is:
>
> cvttss2si 0xffffffd8(%ebp),%eax
>
> Removing the -msse option completely of course clears up the problem but I
> want to use the builtins and the 128 bit vector types available with -msse.
>
> Is there any way as a temporary solution to disable sse code generation but
> still allow use of the builtins?

Please file a complete bug report including a small test program that
shows this behaviour,

Andreas
-- 
 Andreas Jaeger
  SuSE Labs aj@suse.de
   private aj@arthur.inka.de
    http://www.suse.de/~aj

-msse producing sse2 instructions

[Dylan Cuthbert]

Hi there,

I'm having problems compiling with the -msse option and cygwin's latest gcc
(v3.1.1), it seems to be producing SSE2 instructions which my Athlon 4 is
faithfully reporting as illegal instructions.  The athlon 4 should support
standard SSE but not SSE2 instructions.

The current illegal instruction (one of a few others I've had but forgotten
to record) is:

cvttss2si 0xffffffd8(%ebp),%eax

Removing the -msse option completely of course clears up the problem but I
want to use the builtins and the 128 bit vector types available with -msse.

Is there any way as a temporary solution to disable sse code generation but
still allow use of the builtins?

Regards

---------------------------------
Q-Games, Dylan Cuthbert.
http://www.q-games.com