* Insn missing in Size optimization(-Os)
@ 2009-12-02 10:18 daniel tian
2009-12-02 12:29 ` daniel tian
0 siblings, 1 reply; 10+ messages in thread
From: daniel tian @ 2009-12-02 10:18 UTC (permalink / raw)
To: gcc; +Cc: peng.zheng, yan.hu, Dave Korn, Ian Lance Taylor
Hi,
I met a bug in my gcc porting. It work fine when executing with -O0.
But with -Os, there is a insn missed. I dumped the RTL and checked them.
When in movebug.c.175r.lreg, it is fine. But in next phase --
movebug.c.176r.greg, the insn missed.
Here is the simple c program (movebug.c):
void fun() __attribute__((noinline));
void fun()
{
volatile int a=0;
}
int main()
{
int i;
for(i=2; i<16; ++i)
{
fun();
}
return 0;
}
In *.175r.lreg, the RTL code is:
(insn:HI 6 3 8 2 movebug.c:8 (set (reg/v:SI 37 [ i ])
(const_int 2 [0x2])) 2 {constant_load_si} (expr_list:REG_EQUAL
(const_int 2 [0x2])
(nil)))
(insn:HI 8 6 11 2 movebug.c:12 (set (reg/f:SI 42)
(symbol_ref:SI ("fun") [flags 0x3] <function_decl 0xb729ba10
fun>)) 15 {symbolic_address_load} (expr_list:REG_EQUIV (symbol_ref:SI
("fun") [flags 0x3] <function_decl 0xb729ba10 fun>)
(nil)))
(code_label:HI 11 8 7 3 4 "" [1 uses])
(note:HI 7 11 10 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn:HI 10 7 9 3 movebug.c:10 (set (reg/v:SI 37 [ i ])
(plus:SI (reg/v:SI 37 [ i ])
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(call_insn:HI 9 10 13 3 movebug.c:12 (parallel [
(call (mem:SI (reg/f:SI 42) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil))
(nil))
The "fun" function address will be first loaded into register, and
then CALL insn will refer this register which means call the function.
The *.sched1 give the data flow:
;; ======================================================
;; -- basic block 2 from 6 to 8 -- before reload
;; ======================================================
;; 0--> 6 r37=0x2 :nothing
;; 1--> 8 r42=`fun' :nothing
;; Ready list (final):
;; total time = 1
;; new head = 6
;; new tail = 8
;; ======================================================
;; -- basic block 3 from 9 to 13 -- before reload
;; ======================================================
changing bb of uid 10
;; 0--> 10 r37=r37+0x1 :nothing
;; 1--> 9 call [r42] :nothing
;; 2--> 13 pc={(r37!=0x10)?L11:pc} :nothing
;; Ready list (final):
;; total time = 2
;; new head = 10
;; new tail = 13
;; ======================================================
;; -- basic block 4 from 19 to 25 -- before reload
;; ======================================================
;; 0--> 19 R2=0x0 :nothing
;; 1--> 25 use R2 :nothing
;; Ready list (final):
;; total time = 1
;; new head = 19
;; new tail = 25
But in movebug.c.176r.greg, the move function address into a register
insn disappeared. I don't know why the optimization step will take
this insn out of the program, because this will cause a logical error.
(insn:HI 6 3 37 2 movebug.c:8 (set (reg:SI 4 R4)
(const_int 2 [0x2])) 2 {constant_load_si} (expr_list:REG_EQUAL
(const_int 2 [0x2])
(nil)))
(insn 37 6 8 2 movebug.c:8 (set (mem/c:SI (reg/f:SI 15 R15) [3 i+0 S4 A32])
(reg:SI 4 R4)) 8 {store_si} (nil))
(note:HI 8 37 11 2 NOTE_INSN_DELETED)
(code_label:HI 11 8 7 3 4 "" [1 uses])
(note:HI 7 11 38 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 38 7 10 3 movebug.c:10 (set (reg:SI 4 R4)
(mem/c:SI (reg/f:SI 15 R15) [3 i+0 S4 A32])) 11 {load_si} (nil))
(insn:HI 10 38 39 3 movebug.c:10 (set (reg:SI 4 R4)
(plus:SI (reg:SI 4 R4)
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(insn 39 10 9 3 movebug.c:10 (set (mem/c:SI (reg/f:SI 15 R15) [3 i+0 S4 A32])
(reg:SI 4 R4)) 8 {store_si} (nil))
(call_insn:HI 9 39 40 3 movebug.c:12 (parallel [
(call (mem:SI (reg:SI 0 R0) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil))
(nil))
also in movebug.c.194r.sched2, there is an overview of the flowchart:
;; ======================================================
;; -- basic block 2 from 41 to 37 -- after reload
;; ======================================================
;; 0--> 41 [R15-0x4]=R14 :nothing
;; 1--> 42 R0=LINK :nothing
changing bb of uid 44
;; 2--> 44 R15=R15-0xc :nothing
;; 3--> 43 [R14-0x8]=R0 :nothing
changing bb of uid 6
;; 4--> 6 R4=0x2 :nothing
;; 5--> 45 R14=R15 :nothing
;; 6--> 37 [R15]=R4 :nothing
;; Ready list (final):
;; total time = 6
;; new head = 46
;; new tail = 37
;; ======================================================
;; -- basic block 3 from 38 to 13 -- after reload
;; ======================================================
;; 0--> 38 R4=[R15] :rice_load,nothing
;; 2--> 10 R4=R4+0x1 :nothing
;; 3--> 39 [R15]=R4 :nothing
;; 4--> 9 call [R0] :nothing
;; 5--> 40 R4=[R15] :rice_load,nothing
;; 7--> 13 pc={(R4!=0x10)?L11:pc} :nothing
;; Ready list (final):
;; total time = 7
;; new head = 38
;; new tail = 13
;; ======================================================
;; -- basic block 4 from 19 to 52 -- after reload
;; ======================================================
changing bb of uid 48
;; 0--> 48 R15=R14+0xc :nothing
changing bb of uid 50
;; 1--> 50 R0=[R15-0x8] :rice_load,nothing
;; 2--> 19 R2=0x0 :nothing
changing bb of uid 49
;; 3--> 49 R14=[R15-0x4] :rice_load,nothing
;; 4--> 25 use R2 :nothing
;; 4--> 51 LINK=R0 :nothing
;; 5--> 52 return :nothing
;; Ready list (final):
;; total time = 5
;; new head = 47
;; new tail = 52
You can it 's absolutely wrong due to missing R0 assignment. And the
CALL insn will jmp to a incorrect position.
I don't know why it causes this problem. Does anyone also meet this
kind of problem?
Any suggestion is appreciated.
Thanks very much.
daniel.tian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-02 10:18 Insn missing in Size optimization(-Os) daniel tian
@ 2009-12-02 12:29 ` daniel tian
2009-12-02 16:21 ` Ian Lance Taylor
2009-12-02 17:35 ` Jeff Law
0 siblings, 2 replies; 10+ messages in thread
From: daniel tian @ 2009-12-02 12:29 UTC (permalink / raw)
To: gcc; +Cc: peng.zheng, yan.hu, Dave Korn, Ian Lance Taylor
Hi,
Addition information, I just found. It was deleted in function: void
set_insn_deleted (rtx insn), in emit-rtl.c.
It is called by reload() in reload1.c.
Here is the code in reload():
/* If a pseudo has no hard reg, delete the insns that made the equivalence.
If that insn didn't set the register (i.e., it copied the register to
memory), just delete that insn instead of the equivalencing insn plus
anything now dead. If we call delete_dead_insn on that insn, we may
delete the insn that actually sets the register if the register dies
there and that is incorrect. */
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
{
if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
{
rtx list;
for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
{
rtx equiv_insn = XEXP (list, 0);
/* If we already deleted the insn or if it may trap, we can't
delete it. The latter case shouldn't happen, but can
if an insn has a variable address, gets a REG_EH_REGION
note added to it, and then gets converted into a load
from a constant address. */
if (NOTE_P (equiv_insn)
|| can_throw_internal (equiv_insn))
;
else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
delete_dead_insn (equiv_insn);
else
SET_INSN_DELETED (equiv_insn);
}
}
}
But I don't know why the pseudo register can not be fit into a hard
register. The insn :
(insn:HI 8 6 11 2 movebug.c:12 (set (reg/f:SI 42)
(symbol_ref:SI ("fun") [flags 0x3] <function_decl 0xb729ba10
fun>)) 15 {symbolic_address_load} (expr_list:REG_EQUIV (symbol_ref:SI
("fun") [flags 0x3] <function_decl 0xb729ba10 fun>)
(nil)))
is obvious a very useful insn, not a dead one.
So does anybody know why.
Thanks very much.
daniel.tian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-02 12:29 ` daniel tian
@ 2009-12-02 16:21 ` Ian Lance Taylor
2009-12-02 17:35 ` Jeff Law
1 sibling, 0 replies; 10+ messages in thread
From: Ian Lance Taylor @ 2009-12-02 16:21 UTC (permalink / raw)
To: daniel tian; +Cc: gcc, peng.zheng, yan.hu, Dave Korn
daniel tian <daniel.xntian@gmail.com> writes:
> Addition information, I just found. It was deleted in function: void
> set_insn_deleted (rtx insn), in emit-rtl.c.
You need to figure out how register 42 in the call insn got changed to
register 0 if reg_renumber[42] was not set to 0.
Ian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-02 12:29 ` daniel tian
2009-12-02 16:21 ` Ian Lance Taylor
@ 2009-12-02 17:35 ` Jeff Law
2009-12-04 7:01 ` daniel tian
1 sibling, 1 reply; 10+ messages in thread
From: Jeff Law @ 2009-12-02 17:35 UTC (permalink / raw)
To: daniel tian; +Cc: gcc, peng.zheng, yan.hu, Dave Korn, Ian Lance Taylor
On 12/02/09 05:29, daniel tian wrote:
> Hi,
> Addition information, I just found. It was deleted in function: void
> set_insn_deleted (rtx insn), in emit-rtl.c.
> It is called by reload() in reload1.c.
> Here is the code in reload():
>
> /* If a pseudo has no hard reg, delete the insns that made the equivalence.
> If that insn didn't set the register (i.e., it copied the register to
> memory), just delete that insn instead of the equivalencing insn plus
> anything now dead. If we call delete_dead_insn on that insn, we may
> delete the insn that actually sets the register if the register dies
> there and that is incorrect. */
>
> for (i = FIRST_PSEUDO_REGISTER; i< max_regno; i++)
> {
> if (reg_renumber[i]< 0&& reg_equiv_init[i] != 0)
> {
> rtx list;
> for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
> {
> rtx equiv_insn = XEXP (list, 0);
>
> /* If we already deleted the insn or if it may trap, we can't
> delete it. The latter case shouldn't happen, but can
> if an insn has a variable address, gets a REG_EH_REGION
> note added to it, and then gets converted into a load
> from a constant address. */
> if (NOTE_P (equiv_insn)
> || can_throw_internal (equiv_insn))
> ;
> else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
> delete_dead_insn (equiv_insn);
> else
> SET_INSN_DELETED (equiv_insn);
> }
> }
> }
>
> But I don't know why the pseudo register can not be fit into a hard
> register. The insn :
>
> (insn:HI 8 6 11 2 movebug.c:12 (set (reg/f:SI 42)
> (symbol_ref:SI ("fun") [flags 0x3]<function_decl 0xb729ba10
> fun>)) 15 {symbolic_address_load} (expr_list:REG_EQUIV (symbol_ref:SI
> ("fun") [flags 0x3]<function_decl 0xb729ba10 fun>)
> (nil)))
>
> is obvious a very useful insn, not a dead one.
>
When a pseudo which has an equivalent form (via the REG_EQUIV note)
fails to get a hard register, reload deletes the insn which sets the
pseudo and instead will reload the equivalent form into a suitable hard
register prior to use points.
What you want to do is look at the reloads generated for insn #9. I'd
hazard a guess one of them loaded the value (symbol_ref ("fun")) into
R0. Then for some reason (you'll have to figure that out), the reload
insn which sets R0 was deleted (or possibly doesn't get emitted because
reload thought it was unncessary).
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-02 17:35 ` Jeff Law
@ 2009-12-04 7:01 ` daniel tian
2009-12-05 8:01 ` daniel tian
0 siblings, 1 reply; 10+ messages in thread
From: daniel tian @ 2009-12-04 7:01 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc, peng.zheng, yan.hu
> When a pseudo which has an equivalent form (via the REG_EQUIV note) fails to
> get a hard register, reload deletes the insn which sets the pseudo and
> instead will reload the equivalent form into a suitable hard register prior
> to use points.
>
> What you want to do is look at the reloads generated for insn #9. I'd
> hazard a guess one of them loaded the value (symbol_ref ("fun")) into R0.
> Then for some reason (you'll have to figure that out), the reload insn
> which sets R0 was deleted (or possibly doesn't get emitted because reload
> thought it was unncessary).
>
Yeah. The Move Symbol to R0 register is deleted, which is weird.
And I still can not figure out why. Which means I still need to dig it.
But I found when I used the gcc-4.0.2 version, the Call insn call the
function direction
call the function symbol which is OK.
I mean how gcc determine to call the function directly with the function symbol
or move the function symbol ref into a register then call the register.
Obviously, now the gcc-4.3.0 in my porting is working in the latter one.
Do your guys have any advice?
Thanks very much.
best regards.
daniel.tian
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-04 7:01 ` daniel tian
@ 2009-12-05 8:01 ` daniel tian
2009-12-05 16:18 ` Jeff Law
0 siblings, 1 reply; 10+ messages in thread
From: daniel tian @ 2009-12-05 8:01 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc, peng.zheng, yan.hu
[-- Attachment #1: Type: text/plain, Size: 6219 bytes --]
> Yeah. The Move Symbol to R0 register is deleted, which is weird.
> And I still can not figure out why. Which means I still need to dig it.
> But I found when I used the gcc-4.0.2 version, the Call insn call the
> function direction
> call the function symbol which is OK.
> I mean how gcc determine to call the function directly with the function symbol
> or move the function symbol ref into a register then call the register.
> Obviously, now the gcc-4.3.0 in my porting is working in the latter one.
>
I found that gcc will choose to call symbol or register according a
TARGET MACRO --
NO_FUNCTION_CSE. Here is the comment in internal document:
Define this macro if it is as good or better to call a constant
function address than to call an address kept in a register.
Now I defined the macro, the bug disappears. But I still need to know
why gcc delete my insn.
the two insns are in two blocks.
MOV R0 #fun ---in BLOCK 2, this insn is deleted by gcc
CALL R0 ---In Block3
in *.176r.greg:
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(15){ }}
;; lr in 15 [R15]
;; lr use 15 [R15]
;; lr def 0 [R0]
;; live in 15 [R15]
;; live gen 0 [R0]
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 4 2 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 3 4 6 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 6 3 37 2 movebug.c:8 (set (reg:SI 0 R0)
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL
(const_int 0 [0x0])
(nil)))
(insn 37 6 8 2 movebug.c:8 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])
(reg:SI 0 R0)) 8 {store_si} (nil))
(note:HI 8 37 11 2 NOTE_INSN_DELETED)
;; End of basic block 2 -> ( 3)
;; lr out 0 [R0] 15 [R15]
;; live out 0 [R0] 15 [R15]
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 3 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(15){ }}
;; lr in 0 [R0] 15 [R15]
;; lr use 0 [R0] 15 [R15]
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8
[R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18
[LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24
[STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG]
;; live in 0 [R0] 15 [R15]
;; live gen 4 [R4]
;; live kill 17 [LINK]
;; Pred edge 3 [93.8%] (dfs_back)
;; Pred edge 2 [100.0%] (fallthru)
(code_label:HI 11 8 7 3 2 "" [1 uses])
(note:HI 7 11 38 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 38 7 10 3 movebug.c:10 (set (reg:SI 4 R4)
(mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil))
(insn:HI 10 38 39 3 movebug.c:10 (set (reg:SI 4 R4)
(plus:SI (reg:SI 4 R4)
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(insn 39 10 9 3 movebug.c:10 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])
(reg:SI 4 R4)) 8 {store_si} (nil))
(call_insn:HI 9 39 40 3 movebug.c:12 (parallel [
(call (mem:SI (reg:SI 0 R0) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (nil)
(nil))
(insn 40 9 13 3 movebug.c:10 (set (reg:SI 4 R4)
(mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil))
(jump_insn:HI 13 40 14 3 movebug.c:10 (set (pc)
(if_then_else (ne:SI (reg:SI 4 R4)
(const_int 16 [0x10]))
(label_ref:SI 11)
(pc))) 84 {*insn_bne} (expr_list:REG_BR_PROB (const_int
9375 [0x249f])
(nil)))
;; End of basic block 3 -> ( 3 4)
;; lr out 0 [R0] 15 [R15] 17 [LINK]
;; live out 0 [R0] 15 [R15]
in *.175r.lreg:
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP]
;; lr use 14 [R14] 15 [R15] 30 [AP]
;; lr def 37 42
;; live in 14 [R14] 15 [R15] 30 [AP]
;; live gen 37 42
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 4 2 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 3 4 6 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 6 3 8 2 movebug.c:8 (set (reg/v:SI 37 [ i ])
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL
(const_int 0 [0x0])
(nil)))
(insn:HI 8 6 11 2 movebug.c:12 (set (reg/f:SI 42)
(symbol_ref:SI ("fun") [flags 0x41] <function_decl 0xb7257a10
fun>)) 15 {symbolic_address_load} (expr_list:REG_EQUIV (symbol_ref:SI
("fun") [flags 0x41] <function_decl 0xb7257a10 fun>)
(nil)))
;; End of basic block 2 -> ( 3)
;; lr out 14 [R14] 15 [R15] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 3 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u3(14){ }u4(15){ }u5(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr use 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8
[R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18
[LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24
[STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG] 37
;; live in 14 [R14] 15 [R15] 30 [AP] 37 42
;; live gen 37
;; live kill 17 [LINK]
;; Pred edge 3 [93.8%] (dfs_back)
;; Pred edge 2 [100.0%] (fallthru)
(code_label:HI 11 8 7 3 2 "" [1 uses])
(note:HI 7 11 10 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn:HI 10 7 9 3 movebug.c:10 (set (reg/v:SI 37 [ i ])
(plus:SI (reg/v:SI 37 [ i ])
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(call_insn:HI 9 10 13 3 movebug.c:12 (parallel [
(call (mem:SI (reg/f:SI 42) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (nil)
(nil))
(jump_insn:HI 13 9 14 3 movebug.c:10 (set (pc)
(if_then_else (ne:SI (reg/v:SI 37 [ i ])
(const_int 16 [0x10]))
(label_ref:SI 11)
(pc))) 84 {*insn_bne} (expr_list:REG_BR_PROB (const_int
9375 [0x249f])
(nil)))
;; End of basic block 3 -> ( 3 4)
;; lr out 14 [R14] 15 [R15] 17 [LINK] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
those two dump files are attached to this email.
Any advice is appreciated.
Thanks.
Thanks for your guys.
[-- Attachment #2: movebug.c.176r.greg --]
[-- Type: application/octet-stream, Size: 8648 bytes --]
;; Function main (main)
## max_blk: 0
## max_regno: 43
## max_allocno: 2
## Compressed triangular bitmatrix size: 1 bits, 1 bytes
## Standard triangular bitmatrix size: 1 bits, 1 bytes [100.00%]
## Square bitmatrix size: 4 bits, 1 bytes [100.00%]
31 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
32 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
33 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
34 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
35 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
36 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
37 REG_N_REFS=4, REG_FREQ=4000, REG_LIVE_LENGTH=6
38 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
39 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
40 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
41 REG_N_REFS=0, REG_FREQ=0, REG_LIVE_LENGTH=0
42 REG_N_REFS=2, REG_FREQ=2000, REG_LIVE_LENGTH=8
regs_ever_live = 2 15 17
fixed registers : 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30
starting basic block 2
insn = 8 live = hardregs [] renumbered [] pseudos [ 37 42]
adding def 42
roc adding 42<=>(37 42 )
clearing def 42
insn = 6 live = hardregs [] renumbered [] pseudos [ 37]
adding def 37
roc adding 37<=>(37 )
clearing def 37
starting basic block 3
insn = 13 live = hardregs [] renumbered [] pseudos [ 37 42]
seeing use 37
insn = 9 live = hardregs [] renumbered [] pseudos [ 37 42]
adding def 17
clearing def 0
clearing def 1
clearing def 2
clearing def 3
clearing def 4
clearing def 5
clearing def 6
clearing def 7
clearing def 8
clearing def 9
clearing def 10
clearing def 11
clearing def 12
clearing def 13
clearing def 16
clearing def 17
clearing def 18
clearing def 19
clearing def 20
clearing def 21
clearing def 22
clearing def 23
clearing def 24
clearing def 25
clearing def 26
clearing def 27
clearing def 28
clearing def 29
seeing use 15
seeing use 42
insn = 10 live = hardregs [] renumbered [] pseudos [ 37 42]
adding def 37
roc adding 37<=>(37 )
clearing def 37
seeing use 37
dying pseudo
starting early clobber conflicts.
starting basic block 4
insn = 25 live = hardregs [2 ] renumbered [] pseudos []
seeing use 2
insn = 19 live = hardregs [2 ] renumbered [] pseudos []
adding def 2
clearing def 2
;; 2 regs to allocate: 37 42
;; 37 conflicts: 42
;; 42 conflicts: 37
insn=6, live_throughout: 15, dead_or_set:
insn=8, live_throughout: 15, dead_or_set:
insn=11, live_throughout: 15, dead_or_set:
insn=10, live_throughout: 15, dead_or_set:
insn=9, live_throughout: 15, dead_or_set:
insn=13, live_throughout: 15, dead_or_set:
insn=19, live_throughout: 15, dead_or_set: 2
insn=25, live_throughout: 2, 15, dead_or_set:
init_insns for 42: (insn_list:REG_DEP_TRUE 8 (nil))
Spilling for insn 6.
Using reg 4 for reload 0
Spilling for insn 10.
Using reg 4 for reload 1
Spilling for insn 9.
Using reg 0 for reload 0
Spilling for insn 13.
Using reg 4 for reload 0
Spilling for insn 6.
Using reg 4 for reload 0
Spilling for insn 10.
Using reg 4 for reload 1
Spilling for insn 9.
Using reg 0 for reload 0
Spilling for insn 13.
Using reg 4 for reload 0
deleting insn with uid = 8.
Reloads for insn # 6
Reload 0: reload_out (SI) = (reg/v:SI 37 [ i ])
GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:SI 37 [ i ])
reload_reg_rtx: (reg:SI 0 R0)
Reloads for insn # 10
Reload 0: GENERAL_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:SI 37 [ i ])
Reload 1: reload_in (SI) = (reg/v:SI 37 [ i ])
reload_out (SI) = (reg/v:SI 37 [ i ])
GENERAL_REGS, RELOAD_OTHER (opnum = 1)
reload_in_reg: (reg/v:SI 37 [ i ])
reload_out_reg: (reg/v:SI 37 [ i ])
reload_reg_rtx: (reg:SI 4 R4)
Reloads for insn # 9
Reload 0: reload_in (SI) = (symbol_ref:SI ("fun") [flags 0x41] <function_decl 0xb7257a10 fun>)
R0_REG, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), can't combine
reload_in_reg: (reg/f:SI 42)
reload_reg_rtx: (reg:SI 0 R0)
Reloads for insn # 13
Reload 0: reload_in (SI) = (reg/v:SI 37 [ i ])
GENERAL_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (reg/v:SI 37 [ i ])
reload_reg_rtx: (reg:SI 4 R4)
;; Register dispositions:
;; Hard regs used: 0 2 4 15 17
starting the processing of deferred insns
ending the processing of deferred insns
rescanning insn with uid = 9.
deleting insn with uid = 9.
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
df_worklist_dataflow_overeager:n_basic_blocks 5 n_edges 5 count 5 ( 1)
df_worklist_dataflow_overeager:n_basic_blocks 5 n_edges 5 count 6 ( 1.2)
main
Dataflow summary:
;; invalidated by call 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG]
;; hardware regs used 15 [R15]
;; regular block artificial uses 15 [R15]
;; eh block artificial uses 15 [R15] 30 [AP]
;; entry block defs 2 [R2] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 15 [R15]
;; exit block uses 2 [R2] 15 [R15] 17 [LINK]
;; regs ever live 0[R0] 2[R2] 4[R4] 15[R15] 17[LINK]
(note:HI 2 0 4 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u-1(15){ }}
;; lr in 15 [R15]
;; lr use 15 [R15]
;; lr def 0 [R0]
;; live in 15 [R15]
;; live gen 0 [R0]
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 4 2 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 3 4 6 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 6 3 37 2 movebug.c:8 (set (reg:SI 0 R0)
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 37 6 8 2 movebug.c:8 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])
(reg:SI 0 R0)) 8 {store_si} (nil))
(note:HI 8 37 11 2 NOTE_INSN_DELETED)
;; End of basic block 2 -> ( 3)
;; lr out 0 [R0] 15 [R15]
;; live out 0 [R0] 15 [R15]
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 3 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u-1(15){ }}
;; lr in 0 [R0] 15 [R15]
;; lr use 0 [R0] 15 [R15]
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG]
;; live in 0 [R0] 15 [R15]
;; live gen 4 [R4]
;; live kill 17 [LINK]
;; Pred edge 3 [93.8%] (dfs_back)
;; Pred edge 2 [100.0%] (fallthru)
(code_label:HI 11 8 7 3 2 "" [1 uses])
(note:HI 7 11 38 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 38 7 10 3 movebug.c:10 (set (reg:SI 4 R4)
(mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil))
(insn:HI 10 38 39 3 movebug.c:10 (set (reg:SI 4 R4)
(plus:SI (reg:SI 4 R4)
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(insn 39 10 9 3 movebug.c:10 (set (mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])
(reg:SI 4 R4)) 8 {store_si} (nil))
(call_insn:HI 9 39 40 3 movebug.c:12 (parallel [
(call (mem:SI (reg:SI 0 R0) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (nil)
(nil))
(insn 40 9 13 3 movebug.c:10 (set (reg:SI 4 R4)
(mem/c:SI (reg/f:SI 15 R15) [2 i+0 S4 A32])) 11 {load_si} (nil))
(jump_insn:HI 13 40 14 3 movebug.c:10 (set (pc)
(if_then_else (ne:SI (reg:SI 4 R4)
(const_int 16 [0x10]))
(label_ref:SI 11)
(pc))) 84 {*insn_bne} (expr_list:REG_BR_PROB (const_int 9375 [0x249f])
(nil)))
;; End of basic block 3 -> ( 3 4)
;; lr out 0 [R0] 15 [R15] 17 [LINK]
;; live out 0 [R0] 15 [R15]
;; Succ edge 3 [93.8%] (dfs_back)
;; Succ edge 4 [6.2%] (fallthru,loop_exit)
;; Start of basic block ( 3) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u-1(15){ }}
;; lr in 15 [R15] 17 [LINK]
;; lr use 15 [R15]
;; lr def 2 [R2]
;; live in 15 [R15]
;; live gen 2 [R2]
;; live kill
;; Pred edge 3 [6.2%] (fallthru,loop_exit)
(note:HI 14 13 19 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn:HI 19 14 25 4 movebug.c:15 (set (reg/i:SI 2 R2 [ <result> ])
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 25 19 35 4 movebug.c:15 (use (reg/i:SI 2 R2 [ <result> ])) -1 (nil))
;; End of basic block 4 -> ( 1)
;; lr out 2 [R2] 15 [R15] 17 [LINK]
;; live out 2 [R2] 15 [R15]
;; Succ edge EXIT [100.0%] (fallthru)
(note 35 25 36 NOTE_INSN_DELETED)
(note 36 35 0 NOTE_INSN_DELETED)
[-- Attachment #3: movebug.c.175r.lreg --]
[-- Type: application/octet-stream, Size: 8921 bytes --]
;; Function main (main)
starting the processing of deferred insns
ending the processing of deferred insns
df_analyze called
Pass 0
Register 37 costs: R0_REG:0 RETURN_REG:0 RICE_GP_REGS:0 GENERAL_REGS:0 ALL_REGS:8000 MEM:16000
Register 42 costs: R0_REG:0 RETURN_REG:2000 RICE_GP_REGS:2000 GENERAL_REGS:4000 ALL_REGS:4000 MEM:8000
Register 37 pref GENERAL_REGS
Register 42 pref R0_REG
Pass 1
Register 37 costs: R0_REG:0 RETURN_REG:0 RICE_GP_REGS:0 GENERAL_REGS:0 ALL_REGS:8000 MEM:16000
Register 42 costs: R0_REG:0 RETURN_REG:2000 RICE_GP_REGS:2000 GENERAL_REGS:4000 ALL_REGS:4000 MEM:8000
43 registers.
Register 31 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 32 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 33 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 34 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 35 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 36 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.
Register 37 used 4 times across 6 insns; set 2 times; user var; dies in 0 places; crosses 1 call; crosses call with 1000 frequency.
Register 38 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.
Register 39 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none; pointer.
Register 40 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.
Register 41 used 0 times across 0 insns; set 0 times; dies in 0 places; NO_REGS or none.
Register 42 used 2 times across 8 insns; set 1 time; dies in 0 places; crosses 1 call; crosses call with 1000 frequency; pref R0_REG; pointer.
5 basic blocks, 5 edges.
Basic block 0 , next 2, loop_depth 0, count 0, freq 588, maybe hot.
Predecessors:
;; bb 0 artificial_defs: { d4(2){ }d7(4){ }d9(5){ }d11(6){ }d13(7){ }d20(14){ }d21(15){ }d36(30){ }}
;; bb 0 artificial_uses: { }
;; lr in
;; lr use
;; lr def 2 [R2] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 14 [R14] 15 [R15] 30 [AP]
;; live in
;; live gen 2 [R2] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 14 [R14] 15 [R15] 30 [AP]
;; live kill
Successors: 2 [100.0%] (fallthru)
;; lr out 14 [R14] 15 [R15] 30 [AP]
;; live out 14 [R14] 15 [R15] 30 [AP]
Basic block 2 , prev 0, next 3, loop_depth 0, count 0, freq 588, maybe hot.
Predecessors: ENTRY [100.0%] (fallthru)
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP]
;; lr use 14 [R14] 15 [R15] 30 [AP]
;; lr def 37 42
;; live in 14 [R14] 15 [R15] 30 [AP]
;; live gen 37 42
;; live kill
Successors: 3 [100.0%] (fallthru)
;; lr out 14 [R14] 15 [R15] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
Basic block 3 , prev 2, next 4, loop_depth 1, count 0, freq 9412, maybe hot.
Predecessors: 3 [93.8%] (dfs_back) 2 [100.0%] (fallthru)
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u3(14){ }u4(15){ }u5(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr use 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG] 37
;; live in 14 [R14] 15 [R15] 30 [AP] 37 42
;; live gen 37
;; live kill 17 [LINK]
Successors: 3 [93.8%] (dfs_back) 4 [6.2%] (fallthru,loop_exit)
;; lr out 14 [R14] 15 [R15] 17 [LINK] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
Basic block 4 , prev 3, next 1, loop_depth 0, count 0, freq 588, maybe hot.
Predecessors: 3 [6.2%] (fallthru,loop_exit)
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u10(14){ }u11(15){ }u12(30){ }}
;; lr in 14 [R14] 15 [R15] 17 [LINK] 30 [AP]
;; lr use 14 [R14] 15 [R15] 30 [AP]
;; lr def 2 [R2]
;; live in 14 [R14] 15 [R15] 30 [AP]
;; live gen 2 [R2]
;; live kill
Successors: EXIT [100.0%] (fallthru)
;; lr out 2 [R2] 14 [R14] 15 [R15] 17 [LINK] 30 [AP]
;; live out 2 [R2] 14 [R14] 15 [R15] 30 [AP]
Basic block 1 , prev 4, loop_depth 0, count 0, freq 588, maybe hot.
Predecessors: 4 [100.0%] (fallthru)
;; bb 1 artificial_defs: { }
;; bb 1 artificial_uses: { u14(2){ }u15(14){ }u16(15){ }u17(17){ }}
;; lr in 2 [R2] 14 [R14] 15 [R15] 17 [LINK]
;; lr use 2 [R2] 14 [R14] 15 [R15] 17 [LINK]
;; lr def
;; live in 2 [R2] 14 [R14] 15 [R15]
;; live gen
;; live kill
Successors:
;; lr out
;; live out
main
Dataflow summary:
;; invalidated by call 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG]
;; hardware regs used 14 [R14] 15 [R15] 30 [AP]
;; regular block artificial uses 14 [R14] 15 [R15] 30 [AP]
;; eh block artificial uses 14 [R14] 15 [R15] 30 [AP]
;; entry block defs 2 [R2] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 14 [R14] 15 [R15] 30 [AP]
;; exit block uses 2 [R2] 14 [R14] 15 [R15] 17 [LINK]
;; regs ever live 2[R2] 15[R15] 17[LINK]
(note:HI 2 0 4 NOTE_INSN_DELETED)
;; Start of basic block ( 0) -> 2
;; bb 2 artificial_defs: { }
;; bb 2 artificial_uses: { u0(14){ }u1(15){ }u2(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP]
;; lr use 14 [R14] 15 [R15] 30 [AP]
;; lr def 37 42
;; live in 14 [R14] 15 [R15] 30 [AP]
;; live gen 37 42
;; live kill
;; Pred edge ENTRY [100.0%] (fallthru)
(note:HI 4 2 3 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note:HI 3 4 6 2 NOTE_INSN_FUNCTION_BEG)
(insn:HI 6 3 8 2 movebug.c:8 (set (reg/v:SI 37 [ i ])
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn:HI 8 6 11 2 movebug.c:12 (set (reg/f:SI 42)
(symbol_ref:SI ("fun") [flags 0x41] <function_decl 0xb7257a10 fun>)) 15 {symbolic_address_load} (expr_list:REG_EQUIV (symbol_ref:SI ("fun") [flags 0x41] <function_decl 0xb7257a10 fun>)
(nil)))
;; End of basic block 2 -> ( 3)
;; lr out 14 [R14] 15 [R15] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
;; Succ edge 3 [100.0%] (fallthru)
;; Start of basic block ( 3 2) -> 3
;; bb 3 artificial_defs: { }
;; bb 3 artificial_uses: { u3(14){ }u4(15){ }u5(30){ }}
;; lr in 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr use 14 [R14] 15 [R15] 30 [AP] 37 42
;; lr def 0 [R0] 1 [R1] 2 [R2] 3 [R3] 4 [R4] 5 [R5] 6 [R6] 7 [R7] 8 [R8] 9 [R9] 10 [R10] 11 [R11] 12 [R12] 13 [R13] 16 [PC] 17 [LINK] 18 [LINK_S] 19 [STACK] 20 [STACK_S] 21 [LOOP] 22 [LOOP_S] 23 [STATUS] 24 [STATUS_S] 25 [GBR] 26 [GBRCNT] 27 [AMR] 28 [SPARE] 29 [DEBUG] 37
;; live in 14 [R14] 15 [R15] 30 [AP] 37 42
;; live gen 37
;; live kill 17 [LINK]
;; Pred edge 3 [93.8%] (dfs_back)
;; Pred edge 2 [100.0%] (fallthru)
(code_label:HI 11 8 7 3 2 "" [1 uses])
(note:HI 7 11 10 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn:HI 10 7 9 3 movebug.c:10 (set (reg/v:SI 37 [ i ])
(plus:SI (reg/v:SI 37 [ i ])
(const_int 1 [0x1]))) 45 {rice_addsi3} (nil))
(call_insn:HI 9 10 13 3 movebug.c:12 (parallel [
(call (mem:SI (reg/f:SI 42) [0 S4 A32])
(const_int 0 [0x0]))
(clobber (reg:SI 17 LINK))
]) 99 {call} (nil)
(nil))
(jump_insn:HI 13 9 14 3 movebug.c:10 (set (pc)
(if_then_else (ne:SI (reg/v:SI 37 [ i ])
(const_int 16 [0x10]))
(label_ref:SI 11)
(pc))) 84 {*insn_bne} (expr_list:REG_BR_PROB (const_int 9375 [0x249f])
(nil)))
;; End of basic block 3 -> ( 3 4)
;; lr out 14 [R14] 15 [R15] 17 [LINK] 30 [AP] 37 42
;; live out 14 [R14] 15 [R15] 30 [AP] 37 42
;; Succ edge 3 [93.8%] (dfs_back)
;; Succ edge 4 [6.2%] (fallthru,loop_exit)
;; Start of basic block ( 3) -> 4
;; bb 4 artificial_defs: { }
;; bb 4 artificial_uses: { u10(14){ }u11(15){ }u12(30){ }}
;; lr in 14 [R14] 15 [R15] 17 [LINK] 30 [AP]
;; lr use 14 [R14] 15 [R15] 30 [AP]
;; lr def 2 [R2]
;; live in 14 [R14] 15 [R15] 30 [AP]
;; live gen 2 [R2]
;; live kill
;; Pred edge 3 [6.2%] (fallthru,loop_exit)
(note:HI 14 13 19 4 [bb 4] NOTE_INSN_BASIC_BLOCK)
(insn:HI 19 14 25 4 movebug.c:15 (set (reg/i:SI 2 R2 [ <result> ])
(const_int 0 [0x0])) 2 {constant_load_si} (expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn:HI 25 19 35 4 movebug.c:15 (use (reg/i:SI 2 R2 [ <result> ])) -1 (nil))
;; End of basic block 4 -> ( 1)
;; lr out 2 [R2] 14 [R14] 15 [R15] 17 [LINK] 30 [AP]
;; live out 2 [R2] 14 [R14] 15 [R15] 30 [AP]
;; Succ edge EXIT [100.0%] (fallthru)
(note 35 25 0 NOTE_INSN_DELETED)
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-05 8:01 ` daniel tian
@ 2009-12-05 16:18 ` Jeff Law
2009-12-07 3:10 ` daniel tian
0 siblings, 1 reply; 10+ messages in thread
From: Jeff Law @ 2009-12-05 16:18 UTC (permalink / raw)
To: daniel tian; +Cc: gcc, peng.zheng, yan.hu
On 12/05/09 01:01, daniel tian wrote:
>> Yeah. The Move Symbol to R0 register is deleted, which is weird.
>> And I still can not figure out why. Which means I still need to dig it.
>> But I found when I used the gcc-4.0.2 version, the Call insn call the
>> function direction
>> call the function symbol which is OK.
>> I mean how gcc determine to call the function directly with the function symbol
>> or move the function symbol ref into a register then call the register.
>> Obviously, now the gcc-4.3.0 in my porting is working in the latter one.
>>
>>
> I found that gcc will choose to call symbol or register according a
> TARGET MACRO --
> NO_FUNCTION_CSE. Here is the comment in internal document:
> Define this macro if it is as good or better to call a constant
> function address than to call an address kept in a register.
>
Right. When the cost of an indirect call is the same or greater than
the cost of a direct call, then you should define NO_FUNCTION_CSE.
Otherwise you would not define it.
> Now I defined the macro, the bug disappears. But I still need to know
> why gcc delete my insn.
>
Right. You've just papered over the problem. You need to debug reload
and see whether or not the insn is ever emitted into the insn stream and
if so when it gets deleted.
You might start by monitoring emit_reload_insns's behavior when it
handles your insn.
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-05 16:18 ` Jeff Law
@ 2009-12-07 3:10 ` daniel tian
2009-12-08 4:04 ` Jeff Law
0 siblings, 1 reply; 10+ messages in thread
From: daniel tian @ 2009-12-07 3:10 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc, peng.zheng, yan.hu
>
> You might start by monitoring emit_reload_insns's behavior when it handles
> your insn.
I just debug the source code with your advice. Check the function
emit_reload_insns.
That insn was deleted before entering funcion emit_reload_insns. It
was deleted in reload(...) in reload1.c file just before calling
function reload_as_needed(this function will call emit_reload_insns).
It is sure that the insn is generated, but deleted after reload.
insn was deleted in following code.
/* If a pseudo has no hard reg, delete the insns that made the equivalence.
If that insn didn't set the register (i.e., it copied the register to
memory), just delete that insn instead of the equivalencing insn plus
anything now dead. If we call delete_dead_insn on that insn, we may
delete the insn that actually sets the register if the register dies
there and that is incorrect. */
for (i = FIRST_PSEUDO_REGISTER; i < max_regno; i++)
{
if (reg_renumber[i] < 0 && reg_equiv_init[i] != 0)
{
rtx list;
for (list = reg_equiv_init[i]; list; list = XEXP (list, 1))
{
rtx equiv_insn = XEXP (list, 0);
/* If we already deleted the insn or if it may trap, we can't
delete it. The latter case shouldn't happen, but can
if an insn has a variable address, gets a REG_EH_REGION
note added to it, and then gets converted into a load
from a constant address. */
if (NOTE_P (equiv_insn)
|| can_throw_internal (equiv_insn))
;
else if (reg_set_p (regno_reg_rtx[i], PATTERN (equiv_insn)))
delete_dead_insn (equiv_insn); ---->>>>>>>> Call
this function to delete insn.
else
SET_INSN_DELETED (equiv_insn);
}
}
}
I don't know where the reg_equiv_init[i], reg_renumber[i] exactly
changed. I knew the init reg_renumber array is to be -1.
where those arrays' value changed and by what criteria.
I mean I don't know where the gcc thinks this insn is dead, and why dead.
Thanks for your advice.
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-07 3:10 ` daniel tian
@ 2009-12-08 4:04 ` Jeff Law
2009-12-08 6:11 ` daniel tian
0 siblings, 1 reply; 10+ messages in thread
From: Jeff Law @ 2009-12-08 4:04 UTC (permalink / raw)
To: daniel tian; +Cc: gcc, peng.zheng, yan.hu
On 12/06/09 20:10, daniel tian wrote:
>> You might start by monitoring emit_reload_insns's behavior when it handles
>> your insn.
>>
> I just debug the source code with your advice. Check the function
> emit_reload_insns.
>
> That insn was deleted before entering funcion emit_reload_insns. It
> was deleted in reload(...) in reload1.c file just before calling
> function reload_as_needed(this function will call emit_reload_insns).
> It is sure that the insn is generated, but deleted after reload.
>
> insn was deleted in following code.
> /* If a pseudo has no hard reg, delete the insns that made the equivalence.
> If that insn didn't set the register (i.e., it copied the register to
> memory), just delete that insn instead of the equivalencing insn plus
> anything now dead. If we call delete_dead_insn on that insn, we may
> delete the insn that actually sets the register if the register dies
> there and that is incorrect. */
>
No. I'm not referring to why the original insn was deleted. I'm
referring to why the reload insn was deleted (or never emitted in the
first place).
Start by looking at the insns created by emit_reload_insns for the insn
with the call. One of those should be loading a hard register with the
function address.
jeff
^ permalink raw reply [flat|nested] 10+ messages in thread
* Re: Insn missing in Size optimization(-Os)
2009-12-08 4:04 ` Jeff Law
@ 2009-12-08 6:11 ` daniel tian
0 siblings, 0 replies; 10+ messages in thread
From: daniel tian @ 2009-12-08 6:11 UTC (permalink / raw)
To: Jeff Law; +Cc: gcc, peng.zheng, yan.hu
Hi Jeff:
I have already fixed the bug. this occurs due to register
allocation failed in function global_alloc. After calling the
find_reg(), the reg_renumber still keep the value -1 in it. So the
reload() in reload1.c delete the insns.
I didn't set any call saved registers which means every register
is call used. So allocating register failed when
allocno[num].calls_crossed is larger than 0.
This is weird in gcc without sending any warning message.
Anyway, I have to thanks for your guys advice.
Best Wishes.
daniel.tian
^ permalink raw reply [flat|nested] 10+ messages in thread
end of thread, other threads:[~2009-12-08 6:11 UTC | newest]
Thread overview: 10+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2009-12-02 10:18 Insn missing in Size optimization(-Os) daniel tian
2009-12-02 12:29 ` daniel tian
2009-12-02 16:21 ` Ian Lance Taylor
2009-12-02 17:35 ` Jeff Law
2009-12-04 7:01 ` daniel tian
2009-12-05 8:01 ` daniel tian
2009-12-05 16:18 ` Jeff Law
2009-12-07 3:10 ` daniel tian
2009-12-08 4:04 ` Jeff Law
2009-12-08 6:11 ` daniel tian
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