From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31948 invoked by alias); 10 Aug 2009 11:16:39 -0000 Received: (qmail 31935 invoked by uid 22791); 10 Aug 2009 11:16:37 -0000 X-SWARE-Spam-Status: No, hits=-1.0 required=5.0 tests=AWL,BAYES_00,J_CHICKENPOX_32,SPF_PASS X-Spam-Check-By: sourceware.org Received: from cam-admin0.cambridge.arm.com (HELO cam-admin0.cambridge.arm.com) (193.131.176.58) by sourceware.org (qpsmtpd/0.43rc1) with ESMTP; Mon, 10 Aug 2009 11:16:28 +0000 Received: from cam-owa2.Emea.Arm.com (cam-owa2.emea.arm.com [10.1.105.18]) by cam-admin0.cambridge.arm.com (8.12.6/8.12.6) with ESMTP id n7ABGOeI006561 for ; Mon, 10 Aug 2009 12:16:24 +0100 (BST) Received: from [10.1.129.63] ([10.1.255.212]) by cam-owa2.Emea.Arm.com with Microsoft SMTPSVC(6.0.3790.3959); Mon, 10 Aug 2009 12:16:23 +0100 Subject: ifcvt.c question. From: Ramana Radhakrishnan Reply-To: ramana.radhakrishnan@arm.com To: gcc@gcc.gnu.org Content-Type: multipart/mixed; boundary="=-dtaTZOQXYoMG3YGGT8rR" Date: Mon, 10 Aug 2009 12:53:00 -0000 Message-Id: <1249902983.25908.44.camel@e200593-lin.cambridge.arm.com> Mime-Version: 1.0 X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2009-08/txt/msg00157.txt.bz2 --=-dtaTZOQXYoMG3YGGT8rR Content-Type: text/plain Content-Transfer-Encoding: 7bit Content-length: 3909 Hi, While experimenting to see if some of the bits in the ARM backend which do predicated execution can be removed in favour of the more generic bits in ifcvt.c. I attempted to turn on conditional calls using the predicable attribute on the ARM port. I've run into an ICE in the ifcvt pass for the following testcase. typedef int SItype __attribute__ ((mode (SI))); typedef int DItype __attribute__ ((mode (DI))); SItype __mulvsi3 (SItype a, SItype b) { const DItype w = (DItype) a * (DItype) b; if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1)) abort (); return w; } test.c:14:1: internal compiler error: in merge_if_block, at ifcvt.c:2968 Please submit a full bug report, with preprocessed source if appropriate. See for instructions. The ICE is because the following assert fails. /* We cannot merge the JOIN. */ /* The outgoing edge for the current COMBO block should already be correct. Verify this. */ gcc_assert (single_succ_p (combo_bb) && single_succ (combo_bb) == join_bb); Here's what ifcvt does before the crash . IF-THEN block found, pass 1, start block 2 [insn 5], then 3 [14], join 1 [-1] rescanning insn with uid = 15. deleting insn with uid = 15. 1 insn was converted to conditional execution. merging block 3 into block 2 deleting insn with uid = 13. deleting insn with uid = 14. changing bb of uid 15 from 3 to 2 The insns deleted are : (jump_insn 13 12 14 2 test.c:9 (set (pc) (if_then_else (eq (reg:CC 24 cc) (const_int 0 [0x0])) (return) (pc))) 258 {*cond_return} (expr_list:REG_DEAD (reg:CC 24 cc) (expr_list:REG_BR_PROB (const_int 9996 [0x270c]) (nil)))) (note 14 13 15 3 [bb 3] NOTE_INSN_BASIC_BLOCK) insn 15 whose bb is changed from 3 to 2 is the call to abort. (call_insn 15 14 16 3 test.c:10 (parallel [ (call (mem:SI (symbol_ref:SI ("abort") [flags 0x41] ) [0 S4 A32]) (const_int 0 [0x0])) (use (const_int 0 [0x0])) (clobber (reg:SI 14 lr)) ]) 251 {*call_symbol} (expr_list:REG_NORETURN (const_int 0 [0x0]) (expr_list:REG_EH_REGION (const_int 0 [0x0]) (nil))) (nil)) In this case before if-conversion you have a basic block structure of the following form. [2] (cond_return is the last instruction) | [3] (call abort) (REG_EH_NO_RETURN) | [1] - Exit block ifcvt then goes ahead and converts the call to abort into a conditional call and should ideally convert the conditional return as a normal return i.e. by moving the last instruction in [2] into [3] as an unconditional return. It does the first part correctly which is converting the call to a conditional call but incorrectly removes the unconditional return. Note however that thread_prologue_and_epilogue inserts an extra return instruction in basic block 4 but this gets removed by cfg_cleanup the next time it is run before dse2 because bb4 is unreachable. The ARM backend is correct in generating a conditional return in this case, because it is capable of generating a load multiple instruction that restores the PC as well as the saved integer registers. I wonder if the best way to fix this is to teach ifcvt.c to handle conditional returns. Should I be fixing this inside ifcvt.c by handling conditional returns specially or should I be looking elsewhere ? I've attached the dumps and the original patch to turn on the predicable attribute for the ARM backend with this email. Thanks in advance for the answers. cheers Ramana Attachments 1. Patch to turn on predicable attributes on all the ARM call patterns. 2. Dumps of the testcase that are relevant, test.c.*.peephole2, test.c.*.dse2, test.c.*.ce3. (dumps.tar.bz2) 3. Testcase test.c -- Ramana Radhakrishnan GNU Tools ARM Ltd. --=-dtaTZOQXYoMG3YGGT8rR Content-Disposition: attachment; filename=calls_predicable.patch Content-Type: text/x-patch; name=calls_predicable.patch; charset=us-ascii Content-Transfer-Encoding: 7bit Content-length: 2353 Index: arm.md =================================================================== --- arm.md (revision 150565) +++ arm.md (working copy) @@ -4860,7 +4860,8 @@ (define_insn "*arm_movdi" [(set_attr "length" "8,12,16,8,8") (set_attr "type" "*,*,*,load2,store2") (set_attr "pool_range" "*,*,*,1020,*") - (set_attr "neg_pool_range" "*,*,*,1008,*")] + (set_attr "neg_pool_range" "*,*,*,1008,*") + (set_attr "predicable" "yes")] ) (define_split @@ -8446,7 +8447,8 @@ (define_insn "*call_value_reg_armv5" (clobber (reg:SI LR_REGNUM))] "TARGET_ARM && arm_arch5" "blx%?\\t%1" - [(set_attr "type" "call")] + [(set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*call_value_reg_arm" @@ -8460,7 +8462,8 @@ (define_insn "*call_value_reg_arm" return output_call (&operands[1]); " [(set_attr "length" "12") - (set_attr "type" "call")] + (set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*call_value_mem" @@ -8474,7 +8477,8 @@ (define_insn "*call_value_mem" return output_call_mem (&operands[1]); " [(set_attr "length" "12") - (set_attr "type" "call")] + (set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*call_value_reg_thumb1_v5" @@ -8525,7 +8529,8 @@ (define_insn "*call_symbol" { return NEED_PLT_RELOC ? \"bl%?\\t%a0(PLT)\" : \"bl%?\\t%a0\"; }" - [(set_attr "type" "call")] + [(set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*call_value_symbol" @@ -8541,7 +8546,8 @@ (define_insn "*call_value_symbol" { return NEED_PLT_RELOC ? \"bl%?\\t%a1(PLT)\" : \"bl%?\\t%a1\"; }" - [(set_attr "type" "call")] + [(set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*call_insn" @@ -8608,7 +8614,8 @@ (define_insn "*sibcall_insn" "* return NEED_PLT_RELOC ? \"b%?\\t%a0(PLT)\" : \"b%?\\t%a0\"; " - [(set_attr "type" "call")] + [(set_attr "type" "call") + (set_attr "predicable" "yes")] ) (define_insn "*sibcall_value_insn" @@ -8621,7 +8628,8 @@ (define_insn "*sibcall_value_insn" "* return NEED_PLT_RELOC ? \"b%?\\t%a1(PLT)\" : \"b%?\\t%a1\"; " - [(set_attr "type" "call")] + [(set_attr "type" "call") + (set_attr "predicable" "yes")] ) ;; Often the return insn will be the same as loading from memory, so set attr --=-dtaTZOQXYoMG3YGGT8rR Content-Disposition: attachment; filename=dumps.tar.bz2 Content-Type: application/x-bzip-compressed-tar; name=dumps.tar.bz2 Content-Transfer-Encoding: base64 Content-length: 6365 QlpoOTFBWSZTWQsByJgAMvN/pfz8RERSf///v//eev////oIACAIAQACCGAc fffbERIaAAADba0VkGg0CgAAAAAAAAb0rADiAC2ABWgAkAKKoAFBocNAADQa DQGCAGhppkA0NGmQAxA0ADaqoD0/1VGgaAZNGgBpkBkGgGhk0DIGEAAHDQAA 0Gg0BggBoaaZANDRpkAMQNAAiRSjBTyaaCMRtU9T1D0mjQepkaMQGjRoAAHq AHqCKUTam9VR6T00h5TeqaA2mkA0AA0GhoAAGgAGgUqIQ0IaAgEJqeSU/yRi U9ok0PUzU8k8pkeT2qnoT1P1JvSRo3EPydg+LXx605OlxjtlQigTKAgddCDs cuLNl4GeJ8T7i4Llxmrz+7lz5YxyXRc8LlTLKDeTCNiWKhECj60hSGFBYSE2 mYxonjDb0lJjrmhLcdhwwQzsFIxDeCTGxqZNjG88pr/7aGq6YpP7TEGDFTGA xYpgwmn+O/8eb3bY6cAd5qZkwYRnnrOe5PBzNNKuPd/z59rE/6T9fBTSbYm6 FUmIKpOCZF3IpIpIQYoSJSNGCSBdQHEOqJt6KpMsN6MdRs5NWA7F9bVj2tzZ z55Rp0Bphf1BoAHdGIi6Zf4jfWwwwuzgTWecxtw2McDJqamMaarabMrTLEzN J6TWaTWZmszO6eHdP8eEq/csIXNLCkvA/S+EzJG5fz6sdBqsRw5S4gGGCMoa uSBAhCJEpKRuquSDBiRMdq0jv7prPyDvQIHvjArhTxgZg8Jg86+hg7F7j4D4 msbL6jY7j/Ucc4sUyb6j/TfuNizanobGl/SYvT/YfUf+Rgbn3MG3w+rxwzwx 1X3ruOOp7zWMlk0ZH3T7Ptxz7up3nQn55L44D/B4y57nNdv+FRfTSHMOUs3e iGPkBZqgphO0mriUlM/BoFoJe8/pOk0CfIwTJyPtNE0wEwfM+J6xa4mMTnlS zO4nD2az0PM7zSuJiLGBcS4cJpPx5H4d5i1TThfA8PA+dwT45ynhxdebVNGK v3fifjz99kyeB5nqPmY0Op2MnA952OR7jc598Pmmfl3mqHxMKvupiZHv8PDW ejCrmd3mdT1Ov/5g9D1PU8zw9x3RO5PodXzU9f+PBPtMVU4njx1Y8vT4ZPEy bHpydxzCfE4mU8Lnocbnsn3G+Nj5D1H4HBPT4dTmcjZOnb69E48teOqa2CrX xZkjJ0OBmaRR4HM7GvyPganBFuYWHnp9kyzmGJsXcfGr4Vco0LoYPI9DI2GT Iyj7BufgbHkX1n+nkeZsTY9x4HqflP9x4jkXQuKcE3Tmm6apqmqapqmqapqm qaprVk4GknZPZPJO5Nk1TVNU1TVNU1TVNU1TVOKbJunBN04punJOazTnKuRO Sck5JyTgmqapqmqapyTinNOacBlMKHApwhwpHCG0OEN4bw1hrDWGsNYbw3hv DeG8FwTCbpum6ak3TdN03TdNU1TVNU1TdN03TdP3jS+hg/mPjP5jov8vh+ZN O/vnemW7SrTDGHlCHEI9HQh2oHJdBGcqdtP6Tp0TKlaabiTyJbiUwODNoBy8 aOgLjSiarewnmYMTKbzXM107OOtWvfkH884N12x8ZIdSSSdiiqg5BcSQ2siY GWkZqTqgjvet3aEvlv7Fvwyczo13jMaK8J9Xz4JdzvzHVuFsRz1MQoLhFIUE C+mRISicTLi0nAnN559Z2Vrp47d2ndvz/RPmXv+uGE75dfjPlPJO7oPsr3o+ tcfmljgeB2PvPvM+KL8e31L9a3hofpfUzM5ZM4q5NcIVJ3Q1gpsBAQEVhs+F oDsgUCvxN5CjDDhYMYsBg4qZDJhORjPAxiNYpYNB8eRtRbCAXbQsCo2FpAgB kwZGRsLEsKCoHqo8hxZ9ruhsATwhDL9mhe8waftMnLfJ8c5MbHE/krFaWTK0 LEPrMGYaGTLBi/oyytjQ0WK6/5DZYOx4T4mP5ORw6fI/E46jYwczE6YsX1LM vvTE/WOAcjPhrmzZNpzyXI4mZazJjA7GYyeBwcXhz8NMef+b09tOZmZmZv2T A0hOAOmCeYc5L/NWBwwa0Ya6rlrQ4VjOGCxjCPx0U2PU/F+XBLz/GY8fPz8/ T1zw2221+rDxo+E/r9H6Kr6Tv0S/oLslsXM/lJ/Il7ks/sS3nVLQ1nn6T07F rZ/Z4Fo0LA+J4mScE2TkTknmnAcFD2h6pzTdaumJadOZ6w1m/9P580MBMePK kCBAgOgTUMQoHz+b7vtvo5xxQ+ZYTCWUZnTCeWKuZYqzih7YVNJiaJ7TWbT2 nlPSe3nMqnInImRfFMT/mnRMkwnyhiH+gnu6H+efo0K6lgeJZvy5YWDMweJg zkYMnSme84JqngTyTVNinWHkm6aV/FguWhnoR6ZmPny0uqX+cuSaJtIYA7SW JEgkSCRIJEgkSCYmE/25mUxMJibT1TKesPducC4Jim0wmJhOqzMpiYTEwmJh MTCsTCYmExNJxTKcYcdi2TEm+0ymJhMTCaLMymJhMTCYmExP0zSZnFMJxhx4 FsmFK7pYcx1Gs4zWckynKHBqWyYiOLHl0yYb0ztOUzN0ym8NvPbpguKYV576 TlOVbplMp7HEtkwn+3M2nxT/BNmqYTBi34ems4zinFOXK2TBfwZnCcE4Jomy bGZtNk2Teaz4J4ztPfO07pznWe/kTkTW+aYh5JgXRMRYTyhiHVenupC+Z8/W fa8+/z8V0wVgsTODGDHMyLAwbJqmyaGExlOidk0h5Q803TQuGB8NteGybJyM +/E8p7k9yaJwTE1mqap3apsrE2mybJomqYprNU1TRNarnmbTSbJsmqaDE0TR O7W1TFYmqapzLVNU8jE4zgnBNk0miaJrNU1mqapvNp0mJicpvOs75vOs4E9k 0h7JumSYT2hiHedC8uy9iL29qvbh2n+U3nPMyrJYGlgdaYnmmqdicU1ieUPK G0F5pumyjQmGOc5092nLlkuOMMcU4T2T2TRXu1mqapqnTvLaf7y32TSYTEwm 4zMDKZmE8FmZTEwmJwms1TwnKcZrO6d05TeazkTQp70w96apkmE98MQ4Hv8z 3Ve73HgandxOTFgYwYL/iWDyTRPBNMEzKvJOEPGG6eSfnrk5U5Fk+eePLLM1 TPlMpvmfJaJ10mU2zMGUx9ek4aprpMFz0TSYTEwpiYUxOE1ms7pwndNJrOc6 TSaTBPZPZNE5phPaGIde8z56Z64ZMFgeieCaJ0TwTKd0O+HJPBPU24DycOOt j6uot+0yp0MzhorM/wmQ66TKYmE1zMpiYTEwmxmZTE7prNZidZynGd86zrOF cSeaeaaJ0TCecMJzroMHdoeRpz552bTTBjFjqrvTRNKsJyTjDuhyTvTOnBun WYTlmZTExD6ZmYZ9ZpNIaZmYZzMwzmZhnMzDOZ0m04TE6TpOk6zrOs4k7J2T onaHQnbwNjiXfuvL7DgcsGMHcnBNCcU7Jyh3w0TsnZPXnynDjlpDy8ZuaQ01 1mkNNNJpDTM6aQ00mYZ89JtrDXScVpDTK6rWaw1zOU5TimZwnWdZ3TrOk4E8 08U6J5w6E/rWPI61nsYwZzk/Mdydk1J2TuTvh4Q7JzTBgzpwuMwnCcZwnGcp ynKcScSeCeCeEPof7jaeEdTBg6J3pzJ3pwTuh3pxVnY5J1m5lMzCYmExMJkw ZmZvNU5TecpvN5sTYncm6d0P1Y/smP14ff/LlL9QfqGFNTNP4R/IdDBXyXA4 jBobnEfnxTgTCG5/ZVS/iqod8AluA546SXJcmNMaXJclyXJamikoxMTExMTE xMTExMTExMTExMLyVJUkpKSkpKX0lKJRKJRKJRKJKSkpKSkpKSkpKSkpKSkp KMTExMTExMTExMTExMUAoBQCgC0SUokJUlEolEokpKSkpKSkpvN5vNpxnKfR TuX5sr8QTsH6y/vP2x/iar9x++X5yxL8qs1aR/cflH4F0NDAuInAMnznh/WX 5A7zwByMGpX7tDwOxWxmaH/I5Sn/2ax22HVpO4eJgrjg/7lO4wYGBgxVHDjK f+pwP3zx8C9Yy5g8pOp3ep5Ght5GDuOEp4ymh2jgYI4nWWDYesLvNxuP3n9R oe4rB0O42HkdjkXES7R0lNEdZ2K1Ocp8PM4mx6HgdTSPE9Osj5YH9WIGMFhg qJypFEEiRVVtICnGkAXWkFBSJFVHyB3BkGCeanqCWlpIkG7TFEkCpa4JIMCQ CDi/dA2QV95PwJkmpPwJ0J1J0J+BPwJqm5Nybk3JjGJriMGcZrBnBlgnSVdU 7k1TZOqZmYf3nFO5O5O5NOdYx3J0mZ0TmnNOiYVisJhOKc05pzTmncncm6b1 bpum6bpsmybJsmiaJomibJsm6bpum6bpum6bpunWuacIcIcIcIcIbQ5w5w5w 5w3hvDeG8N4bpuTcnBbG3A8B/Lyrcwf3d+TQ2v77W1OJ3mB+0cRxMHM2P2Go 0493dx3+cvpH0DJWD5H6DJoaQpQdcLDthgHonHDaTwJtvk5w3w7p3g7gUF4f SjWnoCsDqQBwkpuMoWhHXCQQs1AXoVf0OK6HTuOLU6GJfQyei7/+C9DBfRcf B+1bL18VGeu0f+E05pyXt/T48Z6kf6JsToPEszhaKPY/32tXJc0941nwmT8h 3TgngRivfOHyNlOP2z5HTE721DmY/sXu3mqOxhXsYTBhjGp/GvlyPBLL8jhK cjVNS/5Jaz4I9g8jBg/1zKWEtj5jA0i1TCfgcDv5TsPeZH0jC8IxT/Ulznmm JirV8zw5w8nxE+XN93gRwhea7HIx5pYPE5MkYnm691O9uziumZiGVemA0pjH 6Z9s+6YmExOf/zJwS+tLko9QTcc2J4mZ/4rbz1Tk5y9MKxMTRGQqQssrWxEv hwxkS0KsVPHt/777e3mToqquNYFWAmCfBfaP0TE/gUySzL8wLSIh0kTWFPoC 5U5hHsjryYpsBmDGUNPbg3yfwmF+WttOs4jjhXBp8Uvm+uHzNHThLiGFGJS2 nh0GsnE7KeMus7HcPlXOd/Lf7zsdTuN9vqmfWYeGX8dGOVXZccq8XtDlVaQd JNY8TtPRheBXYfjO88pfgH2qMp1S+8Jlak+R42nqZOhaUbj4nPzcSO/ovujs 07TFpPZM9EdP6kttx/0WG9VswDhFoMAeKXCdoYm8snBlj1zxHeJ8uK3TthPf tmZhm4zKseuZgfTuS0LSruMGmDgRhTvI96Pi+M1O095zI+g0TUearkl++Xe4 vBLxi/Do1iPCaepJjmdNwbdECDRDAWguMHJpDNAmQJAlSuKwtQgRBsIQEIW0 WqcvJR85s/TDnrFdH2Nuk9pTMu9MnBTC98Z+CPkqxLJ6rBmXj6r3pz4pcfZy pg3k3nvXMrByiuUtYxgjPu6meULbPWMIPVBzO4dS94zV0u81mNoeA8Zol+xM JeRdMHzXe6JsYXY6qOk/Ucj0q7Amst0unNn1k1xZMTGkwxMo8JnKf2mVwOB6 jR1tDvo/njGRpqc2lZylxMQNbuVfKNNFa2NJrKdFcLEw4BORmRlVlgwxOUxN OpsfNyReqYb6xAiA7mxnVC+ngHXAxYhGxGDrRyxmYmFH93Luez2H1J0LeeEx KfUdo6Hf2ldYx18/JVxmKDsmIvnPUYOOR2Tgmx+r2zjYfYVg1+jlV15oxUQH gHQCNBSRYkGhefm7Pa8WVH+01Mj8yfNNZVhMIsJiUwmJhIkEiQSINoDYliWi loFiWTSUaKmiaJoiwmEWEwiwmJTBMRYTmg+8rwUd4/71+9fil4tVcD+4fNXR PtXvimSe769Jqb8Jh7xmYTmPqjoj6efFW0xMJwX5jC00pN/uLYtJh9quU4Vc l9mT8Ta47TpszP4G01XxCGXLhvgsFjvGPfOWiafgvRpD4mJ6sL1MSsA3pfd2 PQ/TV6HkaqczkO0OLxCe8nmosmePijqtc1WQZI71t2rRmua3Oa4JcicBMvfv Ns1Yqti6mStDTCye+YI/1u6NJpX7YxWmkpwmZw/hHP06PpVeeYeNXY8C3I2d Bmuj3zSZqHJbRk24utM4aS0wTAwDZQyo+IPBi78VjzPSOji+rE3P/0ckfxJb J9lTjP0z7F/2zsu6PoYn2R8R1qaxiT5Sx//rhK9/6J7j/ZmfqP7f1zSeaB0M KvtPqn1xXxn3tPzp51eQ2eMzWD3TOwmKnQyCev6ynHBiJ9U+k+DNfNOt4P5r DqL8AQgEyBo7Qqq3BsZqakIwDG9TIucOJzNPKazYofwzEwmCYmIsTCYmKIcS N4X/UXckU4UJALAciYA= --=-dtaTZOQXYoMG3YGGT8rR Content-Disposition: attachment; filename=test.c Content-Type: text/x-csrc; name=test.c; charset=us-ascii Content-Transfer-Encoding: 7bit Content-length: 292 typedef int SItype __attribute__ ((mode (SI))); typedef int DItype __attribute__ ((mode (DI))); void abort (void); SItype __mulvsi3 (SItype a, SItype b) { const DItype w = (DItype) a * (DItype) b; if ((SItype) (w >> (4 * 8)) != (SItype) w >> ((4 * 8) - 1)) abort (); return w; } --=-dtaTZOQXYoMG3YGGT8rR--