Re: condition codes, haifa-sched and virtual-stack-vars

[law@redhat.com]

In message <ms7kpzd371.fsf@mcgary.org>, Greg McGary writes:
 > law@redhat.com writes:
 > 
 > > If arithmetic clobbers the register, then that needs to be reflected in
 > > the RTL for arithmetic.
 > 
 > It is.  FYI, here's the addsi3 pattern:
[ ... ]

 > All other arithmetic patterns are similar.
Got it.


 > Here's a summary of mutations, by optimizer phase.
Thanks.  It was helpful.

I think you're hosed :(


 > Things would have been OK if the stack var weren't the first one,
 > so that it got an offset in 00.rtl, and the associated clobber.
 > Maybe we shouldn't emit bare virtual-stack-vars, but rather emit as
 > plus with 0 offset?
That would be non-canonical RTL.

Fundamentally what we have is a data dependency that isn't exposed until
register allocation -- by which time we've already lost.

What you might consider doing is keeping cc0 setters and cc0 users as a
single insn until after reload.  Once reload is completed, split them
into their component insns.  By the time sched2 runs all the dependencies
are exposed and you shouldn't see any problems.

jeff