From: Oleg Endo <oleg.endo@t-online.de>
To: Hendrik Greving <hendrik.greving.intel@gmail.com>
Cc: gcc@gcc.gnu.org
Subject: Re: Pointer arithmetic
Date: Wed, 07 Aug 2013 20:40:00 -0000 [thread overview]
Message-ID: <1375908001.3952.100.camel@yam-132-YW-E178-FTW> (raw)
In-Reply-To: <CANc4vhov+QRR2PwLSKNZYDyk1d1-hyebHtU23jEap-+bPH-RxQ@mail.gmail.com>
On Tue, 2013-07-09 at 09:37 -0700, Hendrik Greving wrote:
> On a machine with ABI ILP32LL64:
>
> (insn 123 122 124 (nil) (set (reg:SI 392)
> (mem:SI (plus:SI (reg/v:SI 386)
> (reg/v:SI 349)) [0 sec 0 space 0, cmsmode 0 S4 A32])) -1 (nil)
> (nil))
>
> If we support legitimate memory addresses like [r1+r2] (e.g. indexed
> addresses), can the above RTL match such a load?
On 32 bit address machines it should match.
> I am asking because
> of overflows, I am not sure how that part is defined, and where the
> Spec is. What do I need to check in the backend for such a definition?
> Is this POINTER_SIZE? E.g. what if the machine supports > 32 bits, who
> is responsible to make sure that there is no overflow > 32 bits in
> this case? Compiler? Assembler? Or even the user?
AFAIK overflow is undefined and thus anything can happen. Induction
variable and loop optimizations may produce interesting things if
addresses overflow. For example, see
http://gcc.gnu.org/bugzilla/show_bug.cgi?id=55190
Cheers,
Oleg
next prev parent reply other threads:[~2013-08-07 20:40 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2013-07-09 16:37 Hendrik Greving
2013-08-07 20:40 ` Oleg Endo [this message]
2013-08-07 22:43 ` Hendrik Greving
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