* Problem in global register allocation
@ 1997-09-23 4:32 Christian Iseli
1997-09-29 0:05 ` Jeffrey A Law
0 siblings, 1 reply; 6+ messages in thread
From: Christian Iseli @ 1997-09-23 4:32 UTC (permalink / raw)
To: egcs
Hi folks,
I have a problem where the global register allocation pass clobbers the content of a
register. I'm using the 09.22 snapshot. The target is an 8-bit machine. The problem is
shown below; first the RTL after the local register allocation pass:
(insn 371 369 372 (set (reg:QI 109)
(mem/s:QI (plus:HI (reg:HI 93)
(const_int 5)))) 0 {movqi} (nil)
(nil))
(insn 372 371 374 (parallel[
(set (reg/v:HI 25)
(ashift:HI (reg/v:HI 25)
(reg:QI 109)))
(clobber (reg:QI 109))
] ) 83 {*ashlhi3} (insn_list 371 (nil))
(expr_list:REG_UNUSED (reg:QI 109)
(expr_list:REG_EQUAL (ashift:HI (reg/v:HI 25)
(mem/s:QI (plus:HI (reg:HI 93)
(const_int 5))))
(nil))))
===> becomes after global register allocation:
(insn 465 371 372 (set (reg:QI 2 %r2)
(mem:QI (plus:HI (reg:HI 13 %i3h)
(const_int 12)))) -1 (nil)
(nil))
(insn:HI 372 465 463 (parallel[
(set (reg:HI 1 %r3)
(ashift:HI (mem:HI (plus:HI (reg:HI 13 %i3h)
(const_int 10)))
(reg:QI 2 %r2)))
(clobber (reg:QI 2 %r2))
] ) 83 {*ashlhi3} (insn_list 371 (nil))
(expr_list:REG_UNUSED (mem:QI (plus:HI (reg:HI 13 %i3h)
(const_int 12)))
(expr_list:REG_EQUAL (ashift:HI (mem:HI (plus:HI (reg:HI 13 %i3h)
(const_int 10)))
(mem/s:QI (plus:HI (reg:HI 11 %i2h)
(const_int 5))))
(nil))))
Since this is an 8-bit machine, and given the register ordering, hard register (reg:HI 1 %r3)
is composed of registers (reg:QI 1 %r3) and (reg:QI 2 %r2). The problem is that (reg:QI 2 %r2)
is also used and clobbered as specified in the instruction.
Can anybody point me in the direction of where the problem might come from (I find the
global.c and reload*.c files rather obscure...)?
Here is the left shift template FWIW.
(define_insn "*ashlhi3"
[(set (match_operand:HI 0 "register_operand" "=r")
(ashift:HI (match_operand:HI 1 "general_operand" "g")
(match_operand:QI 2 "nonmemory_operand" "ri")))
(clobber (match_dup 2))]
""
"*
{
return output_left_shift(insn, operands, 0);
}")
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Problem in global register allocation
1997-09-23 4:32 Problem in global register allocation Christian Iseli
@ 1997-09-29 0:05 ` Jeffrey A Law
1997-09-29 2:29 ` Andreas Schwab
0 siblings, 1 reply; 6+ messages in thread
From: Jeffrey A Law @ 1997-09-29 0:05 UTC (permalink / raw)
To: Christian Iseli; +Cc: egcs
In message < 199709231131.NAA05089@lslsun17.epfl.ch >you write:
> Here is the left shift template FWIW.
>
> (define_insn "*ashlhi3"
> [(set (match_operand:HI 0 "register_operand" "=r")
> (ashift:HI (match_operand:HI 1 "general_operand" "g")
> (match_operand:QI 2 "nonmemory_operand" "ri")))
> (clobber (match_dup 2))]
Try changing the mode of operand 2 to HImode.
In general, mixing modes like that in patterns has lead to problems
in the past and should be avoided. I've also seen mixing modes like
that pessimize code, though I didn't investigate why.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Problem in global register allocation
1997-09-29 0:05 ` Jeffrey A Law
@ 1997-09-29 2:29 ` Andreas Schwab
1997-09-29 8:35 ` Jeffrey A Law
0 siblings, 1 reply; 6+ messages in thread
From: Andreas Schwab @ 1997-09-29 2:29 UTC (permalink / raw)
To: law; +Cc: Christian Iseli, egcs
Jeffrey A Law <law@cygnus.com> writes:
|> In message < 199709231131.NAA05089@lslsun17.epfl.ch >you write:
|> > Here is the left shift template FWIW.
|> >
|> > (define_insn "*ashlhi3"
|> > [(set (match_operand:HI 0 "register_operand" "=r")
|> > (ashift:HI (match_operand:HI 1 "general_operand" "g")
|> > (match_operand:QI 2 "nonmemory_operand" "ri")))
|> > (clobber (match_dup 2))]
|> Try changing the mode of operand 2 to HImode.
Why? The size of the shift count has nothing to do with the size of the
shifted value. For example, on the m68k the shift count is truncated to 5
bits by the cpu. It doesn't make sense to require anything wider.
|> In general, mixing modes like that in patterns has lead to problems
|> in the past and should be avoided. I've also seen mixing modes like
|> that pessimize code, though I didn't investigate why.
Actually, making the shift count wider may pessimize the code, in case it
has to be widened to match the constraint. Of course, this is pretty
unlikely, but truncating a value comes for free on most, if not all cpus.
--
Andreas Schwab "And now for something
schwab@issan.informatik.uni-dortmund.de completely different"
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Problem in global register allocation
1997-09-29 2:29 ` Andreas Schwab
@ 1997-09-29 8:35 ` Jeffrey A Law
0 siblings, 0 replies; 6+ messages in thread
From: Jeffrey A Law @ 1997-09-29 8:35 UTC (permalink / raw)
To: Andreas Schwab; +Cc: Christian Iseli, egcs
In message < vyzg1qoo4d1.fsf@issan.informatik.uni-dortmund.de >you write:
> |> Try changing the mode of operand 2 to HImode.
>
> Why? The size of the shift count has nothing to do with the size of the
> shifted value. For example, on the m68k the shift count is truncated to 5
> bits by the cpu. It doesn't make sense to require anything wider.
No reason other than I've personally had problems mixing modes
like that.
> Actually, making the shift count wider may pessimize the code, in case it
> has to be widened to match the constraint. Of course, this is pretty
> unlikely, but truncating a value comes for free on most, if not all cpus.
True. The difference is I'm speaking from actual experience -- I've
actually seen mixing modes in the manner Christian is doing pessimize
code.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Problem in global register allocation
1997-09-29 1:53 Christian Iseli
@ 1997-09-29 8:35 ` Jeffrey A Law
0 siblings, 0 replies; 6+ messages in thread
From: Jeffrey A Law @ 1997-09-29 8:35 UTC (permalink / raw)
To: Christian Iseli; +Cc: egcs
In message < 199709290853.KAA08455@lslsun17.epfl.ch >you write:
> That might avoid the problem, though I didn't check.
It's worth checking.
> Well, it seems I'm not the only one to use such a scheme, the h8300 target
> uses it as well, and maybe others too.
H8 and mn10200.
jeff
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Problem in global register allocation
@ 1997-09-29 1:53 Christian Iseli
1997-09-29 8:35 ` Jeffrey A Law
0 siblings, 1 reply; 6+ messages in thread
From: Christian Iseli @ 1997-09-29 1:53 UTC (permalink / raw)
To: law; +Cc: egcs
> Try changing the mode of operand 2 to HImode.
That might avoid the problem, though I didn't check.
> In general, mixing modes like that in patterns has lead to problems
> in the past and should be avoided. I've also seen mixing modes like
> that pessimize code, though I didn't investigate why.
Well, it seems I'm not the only one to use such a scheme, the h8300 target
uses it as well, and maybe others too. The thing is that I'm compiling
for a small 8-bit micro with precious few registers. Using 2 or even 4
registers when one is plenty is a *bad* thing on such a beast. I'd rather
try to fix the compiler than put a kludge in the machine description, though
of course, that might not be easy. Any pointer as to where the problem might
come from would be greatly appreciated...
Christian
^ permalink raw reply [flat|nested] 6+ messages in thread
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1997-09-23 4:32 Problem in global register allocation Christian Iseli
1997-09-29 0:05 ` Jeffrey A Law
1997-09-29 2:29 ` Andreas Schwab
1997-09-29 8:35 ` Jeffrey A Law
1997-09-29 1:53 Christian Iseli
1997-09-29 8:35 ` Jeffrey A Law
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