Re: some Sparc hackery in the works

[Jeffrey A Law <law@cygnus.com>]

  In message < 199807131854.TAA18918@phal.cygnus.co.uk >you write:
  > You usually get worse code if you try to open-code DImode operations as
  > RTL at rtl generation time.
This depends on numerous factors, including but not limited to how many
registers the target has and how important scheduling is for good performance
on the target.

  > You can get the same benefit for scheduling and delay slot filling if you
  > povide define_splits for the patterns in question; you can then also
  > safe the output template by replacing it with a '#', to indicate that
  > this pattern must be split.
Not necessarily since you lose optimizations done by various other
optimizers.  For example, the sub-parts of a DImode load become
candidates for CSE, GCSE, combine, local alloc, etc.

There's generally some tradeoff for each direction.  We should trust
David to do the right thing for the sparc port.

jeff

ps.  Much of Dave's work mirrors stuff rth and myself have discussed
as important to handle better on the sparc port.