From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 17862 invoked by alias); 14 Oct 2002 10:54:22 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 17479 invoked from network); 14 Oct 2002 10:54:19 -0000 Received: from unknown (HELO fencepost.gnu.org) (199.232.76.164) by sources.redhat.com with SMTP; 14 Oct 2002 10:54:19 -0000 Received: from monty-python.gnu.org ([199.232.76.173]) by fencepost.gnu.org with esmtp (Exim 4.10) id 1812rb-0003g1-01 for gcc@gnu.org; Mon, 14 Oct 2002 06:54:19 -0400 Received: from mail by monty-python.gnu.org with spam-scanned (Exim 4.10) id 1812oI-0007ou-00 for gcc@gnu.org; Mon, 14 Oct 2002 06:50:56 -0400 Received: from dell-paw-3.cambridge.redhat.com ([195.224.55.237] helo=executor.cambridge.redhat.com) by monty-python.gnu.org with esmtp (Exim 4.10) id 1812oI-0007oo-00 for gcc@gnu.org; Mon, 14 Oct 2002 06:50:54 -0400 Received: from cuddles.cambridge.redhat.com (vpn50-1.rdu.redhat.com [172.16.50.1]) by executor.cambridge.redhat.com (Postfix) with ESMTP id 53259ABB0B; Mon, 14 Oct 2002 11:50:51 +0100 (BST) Received: (from aph@localhost) by cuddles.cambridge.redhat.com (8.11.6/8.11.0) id g9EAptf07073; Mon, 14 Oct 2002 11:51:55 +0100 From: Andrew Haley MIME-Version: 1.0 Content-Type: text/plain; charset=us-ascii Content-Transfer-Encoding: 7bit Message-ID: <15786.41419.795898.346171@cuddles.cambridge.redhat.com> Date: Mon, 14 Oct 2002 07:45:00 -0000 To: N V Krishna Cc: gcc@gnu.org Subject: load multiple In-Reply-To: References: X-Spam-Status: No, hits=-4.7 required=5.0 tests=IN_REP_TO,REFERENCES,SPAM_PHRASE_00_01 version=2.41 X-Spam-Level: X-SW-Source: 2002-10/txt/msg00690.txt.bz2 N V Krishna writes: > Hi, > I am working on a ARM port of gcc. I want to insert 'load > multiple' instructions in the code. If the registers are sequential then I > can see the function arm_gen_load_multiple. But I am unable to insert > instructions , where the destination registers list is not sequential. > > ldmea r1,{r2,r5} > > Can anyone suggest the debug_rtl output for the above type of instruction? Can't you use just run ARM gcc and dump the RTL to see what it looks like? Andrew.