From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jeffrey A Law <law@cygnus.com>
To: ak@muc.de
Cc: egcs@cygnus.com
Subject: Re: Feature request: ability to describe x86 register halves as contraints. 
Date: Tue, 30 Jun 1998 01:02:00 -0000
Message-id: <15971.899192800@hurl.cygnus.com>
References: <19980629184404.62482@kali.lrz-muenchen.de>
X-SW-Source: 1998-06/msg01107.html

  In message < 19980629184404.62482@kali.lrz-muenchen.de >you write:
  > Egcs does not handle x86 register halves (al/ah etc.) well. Although
  > it is able to turn (x & 0xFF) into an access to the rL register, there
  > is no way to trick it into generating write access to rH registers
  > (neither union { char h,l; short val } x; x.h = 1; nor and/shift/or tricks
  > work). 
The lack of aggressive use of byte/half sized registers is probably
a direct result of the x86 target files being designed as a 32bit
target.

It claims registers are 32bits wide and that the size of a word is
32bits.

To get more aggressive optimziation of these smaller values you'd have
to change the size of registers.  A *large* task.  I looked into doing
it for the H8 a while back and decided it was not worth the effort.

One could argue that gcc should have better mechanisms to deal with
partial registers.

Such concepts would help many older ports like the x86, m68k, h8, etc.

[ ... ]
  > Is it possible to add such an extension to the constraints language? 
  > Hopefully only minimal changes should be needed for this. 
First there'd have to be a way to describe hi/lo halves of registers
in RTL.  I'm not aware of any such mechanism.

jeff