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[124.171.74.249]) by smtp.gmail.com with ESMTPSA id y23-20020a1709029b9700b0015e8d4eb2c0sm279342plp.266.2022.05.20.17.11.53 (version=TLS1_3 cipher=TLS_AES_256_GCM_SHA384 bits=256/256); Fri, 20 May 2022 17:11:54 -0700 (PDT) Date: Sat, 21 May 2022 10:11:48 +1000 From: Nicholas Piggin Subject: Re: [RFC Linux patch] powerpc: add documentation for HWCAPs To: linuxppc-dev@lists.ozlabs.org, Paul E Murphy Cc: gcc@gcc.gnu.org, libc-alpha@sourceware.org References: <20220520051528.98097-1-npiggin@gmail.com> In-Reply-To: MIME-Version: 1.0 Message-Id: <1653091346.1a5h1ae3pd.astroid@bobo.none> Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: quoted-printable X-Spam-Status: No, score=-2.2 required=5.0 tests=BAYES_00, DKIM_SIGNED, DKIM_VALID, DKIM_VALID_AU, DKIM_VALID_EF, FREEMAIL_FROM, RCVD_IN_DNSWL_NONE, SPF_HELO_NONE, SPF_PASS, TXREP, T_SCC_BODY_TEXT_LINE autolearn=ham autolearn_force=no version=3.4.6 X-Spam-Checker-Version: SpamAssassin 3.4.6 (2021-04-09) on server2.sourceware.org X-BeenThere: gcc@gcc.gnu.org X-Mailman-Version: 2.1.29 Precedence: list List-Id: Gcc mailing list List-Unsubscribe: , List-Archive: List-Post: List-Help: List-Subscribe: , X-List-Received-Date: Sat, 21 May 2022 00:11:57 -0000 Excerpts from Paul E Murphy's message of May 21, 2022 12:21 am: >=20 >=20 > On 5/20/22 12:15 AM, Nicholas Piggin via Gcc wrote: >> This takes the arm64 file and adjusts it for powerpc. Feature >> descriptions are vaguely handwaved by me. >> --- >>=20 >> Anybody care to expand on or correct the meaning of these entries or >> bikeshed the wording of the intro? Many of them are no longer used >> anywhere by upstream kernels and even where they are it's not always >> quite clear what the exact intent was, a lot of them are old history >> and I don't know what or where they are used. >>=20 >> I may try to get these descriptions pushed into the ABI doc after a >> time, but for now they can live in the kernel tree. >>=20 >> Thanks, >> Nick >=20 > Thanks, this is really helpful. I've been caught off-guard by some of=20 > the subtleties in the meanings of these bits at times. I think it would=20 > be helpful to share what is implied by the usage of the word "facility"=20 > below. It would resolve some of my questions below. Yeah that's probably a good point. In the introduction we can explain that the facility is a class of instructions, registers, and behaviour, but that the specifics depend on the ISA version. >=20 >=20 >=20 >> +PPC_FEATURE_HAS_ALTIVEC >> + Vector (aka Altivec, VSX) facility is available. >=20 > I think "(aka Altivec, VSX)" might be more accurately stated as "(aka=20 > Altivec)"? Yes VSX is a thinkso, should be VMX as pointed out. >> +PPC_FEATURE_HAS_DFP >> + DFP facility is available. >=20 > Maybe something like "Decimal floating point instructions are available=20 > to userspace. Individual instruction availability is dependent on the > reported architecture version."? Yep, we can cover all these with a note in the intro. >> +PPC_FEATURE_HAS_VSX >> + VSX facility is available. > A small reminder the features are also dependent on architecture version=20 > too might be helpful here too. >=20 >=20 >> +PPC_FEATURE2_TAR >> + VSX facility is available. >=20 > Was manipulating the tar spr was once a privileged instruction, is this=20 > a hint userspace can use the related instructions? It can be disabled with facility control, and I guess there was some consideration for how it might be used, e.g., "system software" could use it for its own purpose then clear the bit for the application. In practice I don't really know what makes use of this or whether anything sanely can, it's marked reserved in the ABI. Would be=20 interesting to know whether there is much benefit to use it in the compiler. The kernel could actually use it for something nifty if we were able to prevent userspace from accessing it entirely... >> + >> +PPC_FEATURE2_HAS_IEEE128 >> + IEEE 128 is available? What instructions/data? >=20 > Maybe something like "IEEE 128 binary floating point instructions are=20 > supported. Individual instruction availability is dependent on the > reported architecture version."? Right, I just didn't know what architectural class of instructions those are. Is it just VSX in general or are there some specific things we can name? >> +PPC_FEATURE2_SCV >> + scv instruction is available. >=20 > I think it might be clearer to say "This kernel supports syscalls using=20 > the scv instruction". Yeah good point. >> +PPC_FEATURE2_MMA >> + MMA facility is available. >=20 > Maybe another note that specific instruction availability may depend on=20 > the reported architecture version? Thanks, Nick