From: "Michael P. Hayes" <michaelh@ongaonga.chch.cri.nz>
To: law@cygnus.com
Cc: meissner@cygnus.com, michaelh@ongaonga.chch.cri.nz,
egcs@cygnus.com, gcc2@cygnus.com
Subject: Re: base + index register addressing
Date: Fri, 17 Oct 1997 20:51:00 -0000 [thread overview]
Message-ID: <199710172339.MAA26949@ongaonga.chch.cri.nz> (raw)
In-Reply-To: <11680.877104611@hurl.cygnus.com>
Jeffrey A Law writes:
> > I was going to comment that the patch might be even better, if it
> > dealt with register + scaled register that some machines have (such
> > as the x86, ns32k, 88k to name the ones I've dealt with).
> It's worth noting that patch only helps when the base/index is a hard reg,
> which limits its usefulness on most of our platforms. It's unclear if
> the benefit for handling scaled register would outweigh the work involved.
Most of the utility of the patch occurs when an incoming function
argument is in a hard base (or possibly index) register.
IMO, things would be simpler if two register addresses were
canonicalized so that the base register preceeded the index register,
i.e., (mem (plus (base_reg) (index_reg)). This would reduce the
ambiguity when it comes to allocating base and index registers.
mph...
next prev parent reply other threads:[~1997-10-17 20:51 UTC|newest]
Thread overview: 12+ messages / expand[flat|nested] mbox.gz Atom feed top
1997-10-17 12:53 meissner
1997-10-17 13:57 ` Jeffrey A Law
1997-10-17 20:51 ` Michael P. Hayes [this message]
1997-10-17 21:40 ` Jeffrey A Law
1997-10-20 9:43 ` Nick Ing-Simmons
1997-10-20 18:12 ` Joern Rennecke
1997-10-21 8:49 ` Nick Ing-Simmons
1997-10-21 9:25 ` John Carr
1997-10-17 12:53 meissner
1997-10-17 13:57 ` Jeffrey A Law
1997-10-17 20:51 ` Richard Henderson
[not found] <199710170919.WAA23619@ongaonga.chch.cri.nz>
1997-10-17 13:57 ` Jeffrey A Law
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