From mboxrd@z Thu Jan 1 00:00:00 1970 From: "Michael P. Hayes" To: law@cygnus.com Cc: meissner@cygnus.com, michaelh@ongaonga.chch.cri.nz, egcs@cygnus.com, gcc2@cygnus.com Subject: Re: base + index register addressing Date: Fri, 17 Oct 1997 20:51:00 -0000 Message-id: <199710172339.MAA26949@ongaonga.chch.cri.nz> References: <199710171559.LAA25330@tweedledumb.cygnus.com> <11680.877104611@hurl.cygnus.com> X-SW-Source: 1997-10/msg00783.html Jeffrey A Law writes: > > I was going to comment that the patch might be even better, if it > > dealt with register + scaled register that some machines have (such > > as the x86, ns32k, 88k to name the ones I've dealt with). > It's worth noting that patch only helps when the base/index is a hard reg, > which limits its usefulness on most of our platforms. It's unclear if > the benefit for handling scaled register would outweigh the work involved. Most of the utility of the patch occurs when an incoming function argument is in a hard base (or possibly index) register. IMO, things would be simpler if two register addresses were canonicalized so that the base register preceeded the index register, i.e., (mem (plus (base_reg) (index_reg)). This would reduce the ambiguity when it comes to allocating base and index registers. mph...