From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joern Rennecke <amylaar@cygnus.co.uk>
To: michaelh@ongaonga.chch.cri.nz (Michael P. Hayes)
Cc: rth@cygnus.com, amylaar@cygnus.co.uk, michaelh@ongaonga.chch.cri.nz, egcs@cygnus.com
Subject: Re: Autoincrement addressing modes
Date: Mon, 16 Mar 1998 20:25:00 -0000
Message-id: <199803170004.AAA09012@phal.cygnus.co.uk>
References: <199803170002.AAA24152@ongaonga.chch.cri.nz>
X-SW-Source: 1998-03/msg00549.html

>  > I thought I'd had a pseudo example of what I'd had in mind for handling
>  > both of these in a stroke: referencing it in an insn.
>  > 
>  >   (define_insn "*movsi_load"
>  >     [(set (match_operand:SI 0 "register_operand" "r")
>  > 	  (mem:SI (match_address:PI 1 "base,base_disp,auto_inc")))]
>  >     "ldl %0,%1")
>  > 
>  >   (define_insn "*movsi_store"
>  >     [(set (mem:SI (match_address:PI 1 "base,base_disp,auto_dec"))
>  > 	  (match_operand:SI 0 "register_operand" "r"))]
>  >     "stl %0,%1")
>  > 
> 
> I'm unsure about this since it would require wholesale changes to the
> machine description.  For example, how would you handle an add insn
> that could have memory or register operands in various combinations?

Seconded.  This even applies to some RISC pattern, e.g. sign/zero extension
can be a register-register operation or a memory-register operation.
The way gcc is designde we have to use a single pattern for this so that
reload can do The Right Thing (tm).