From mboxrd@z Thu Jan  1 00:00:00 1970
From: kkaempf@progis.de
To: egcs@cygnus.com
Subject: egcs 2.91.14: packed-1 failure on openvms/alpha, more info
Date: Wed, 18 Mar 1998 14:08:00 -0000
Message-id: <19980318140040.1552.qmail@progis.de>
X-SW-Source: 1998-03/msg00603.html

Looks like there is a bug in simplify_shift_const() (combine.c)
for mixed 32/64 bit targets.

It is called from alpha_expand_unaligned_load() in alpha/alpha.c
for the signed word case (see comment there).

Adding a bit of debug output reveals a wrong simplification

simplify_shift_const (code 81(ashiftrt), mode 6(DI), count 48)

x:	(ashiftrt:DI (and:DI (reg:DI 82)
	        (const_int -281474976710656 0xffff000000000000))
	    (const_int 48 0x30))

varop:	(and:DI (reg:DI 82)
	    (const_int -281474976710656 0xffff000000000000))

returns
 
	(ashiftrt:DI (reg:DI 82)
	    (const_int 63 0x3f))


So instead of removing the (unneeded) 'and' operation from the
ashiftrt operand, the shift count is set to the wrong value.

The code in question is at line 8338 in combine.c:

      /* If we are doing an arithmetic right shift and discarding all but
         the sign bit copies, this is equivalent to doing a shift by the
         bitsize minus one.  Convert it into that shift because it will often
         allow other simplifications.  */
      
      if (code == ASHIFTRT
          && (count + num_sign_bit_copies (varop, shift_mode)
              >= GET_MODE_BITSIZE (shift_mode)))
        count = GET_MODE_BITSIZE (shift_mode) - 1;
         
since num_sign_bit_copies() returns 16 and count is set to 63.

Klaus
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