From mboxrd@z Thu Jan  1 00:00:00 1970
From: Jim Wilson <wilson@cygnus.com>
To: Richard Henderson <rth@cygnus.com>
Cc: egcs@cygnus.com
Subject: Re: alpha failure on 920810-1 
Date: Tue, 28 Apr 1998 22:14:00 -0000
Message-id: <199804290430.VAA25220@rtl.cygnus.com>
References: <19980427014147.34497@dot.cygnus.com>
X-SW-Source: 1998-04/msg01135.html

	The reason is that the limited comparison
	done by the conditional move does not follow all of the IEEE rules
	that the comparision insn does, but rather simply test that the
	register has no bits set.

I suspect that there are no currently supported machines for which your
get_condition change is wrong, but there may be future architectures for
which is it wrong.  In any case, it doesn't seem to really fix the problem.
For instance, you will probably see the same invalid transformations from
combine.  Fixing loop doesn't help with that.

To fix this elegantly, we need to make the RTL operations distinct if
they are performing different operations.  Since we can't do this with
CCmodes, it seems to imply that we need new comparison operators.  For
instance, perhaps we need eqieee separate from eq, similar to how gtu is
separate from gt.  This would require changing a lot of code though to
handle the new operators though.  That would be a major task.

Adding a strategic unspec operation could fix the problem, at the expense
of uglifying the alpha.md file a bit, and perhaps losing some optimizations.
It is likely a simpler solution though.

I don't see any clean and simple way to fix the problem.

Jim