From mboxrd@z Thu Jan  1 00:00:00 1970
From: Joern Rennecke <amylaar@cygnus.co.uk>
To: wilson@cygnus.com (Jim Wilson)
Cc: rth@cygnus.com, egcs@cygnus.com
Subject: Re: alpha failure on 920810-1
Date: Wed, 29 Apr 1998 16:08:00 -0000
Message-id: <199804292113.WAA32444@phal.cygnus.co.uk>
References: <199804290430.VAA25220@rtl.cygnus.com>
X-SW-Source: 1998-04/msg01168.html

> 	The reason is that the limited comparison
> 	done by the conditional move does not follow all of the IEEE rules
> 	that the comparision insn does, but rather simply test that the
> 	register has no bits set.
...
> To fix this elegantly, we need to make the RTL operations distinct if
> they are performing different operations.  Since we can't do this with
> CCmodes, it seems to imply that we need new comparison operators.  For
> instance, perhaps we need eqieee separate from eq, similar to how gtu is
> separate from gt.  This would require changing a lot of code though to
> handle the new operators though.  That would be a major task.
> 
> Adding a strategic unspec operation could fix the problem, at the expense
> of uglifying the alpha.md file a bit, and perhaps losing some optimizations.
> It is likely a simpler solution though.

If it tests only if all bits are zero, I think we should express this
as a DImode equality test to zero:

        (set (reg:DF 1)
          (eq:DF (reg:DF 2) (reg:DF 3)))
        (set (reg:DF 4)
          (if_then_else:DF (eq (subreg:DI (reg:DF 1) 0)
                               (const_int 0))
                           (reg:DF 5)
                           (reg:DF 4)))