From mboxrd@z Thu Jan  1 00:00:00 1970
From: Michael Hayes <michaelh@ongaonga.chch.cri.nz>
To: Joern Rennecke <amylaar@cygnus.co.uk>
Cc: davem@dm.cobaltmicro.com (David S. Miller), egcs@cygnus.com
Subject: Re: some Sparc hackery in the works
Date: Mon, 13 Jul 1998 20:56:00 -0000
Message-id: <199807140358.DAA10524@ongaonga.chch.cri.nz>
References: <199807131107.EAA11110@dm.cobaltmicro.com> <199807131854.TAA18918@phal.cygnus.co.uk>
X-SW-Source: 1998-07/msg00469.html

Joern Rennecke writes:
 > You usually get worse code if you try to open-code DImode operations as
 > RTL at rtl generation time.

Yep, I fell into that trap.  The register allocator does a very poor
job with SUBREGs.

 > You can get the same benefit for scheduling and delay slot filling if you
 > povide define_splits for the patterns in question; you can then also
 > safe the output template by replacing it with a '#', to indicate that
 > this pattern must be split.

Snippets of advice, such as this, should be in the manual somewhere.
The only drawback to this approach I found was that it was harder to
peer inside these composite insns to check for register usage.