From mboxrd@z Thu Jan 1 00:00:00 1970 From: Richard Henderson To: law@cygnus.com, Jerry Quinn Cc: egcs@egcs.cygnus.com Subject: Re: Fwd: Questions on PA machine description? Date: Fri, 19 Mar 1999 17:32:00 -0000 Message-id: <19990319173226.C14722@cygnus.com> In-reply-to: < 18375.921819620@hurl.cygnus.com >; from Jeffrey A Law on Thu, Mar 18, 1999 at 10:00:20PM -0700 References: <36F17F8C.9FD937FA@americasm01.nt.com> <18375.921819620@hurl.cygnus.com> <18375.921819620@hurl.cygnus.com> X-SW-Source: 1999-03/msg00681.html On Thu, Mar 18, 1999 at 10:00:20PM -0700, Jeffrey A Law wrote: > It has a structure like: > > while (not all insns scheduled) > add insns with no outstanding dependencies to the ready queue > sort the ready queue > while (ready list is not empty && target can issue more insns) > issue an insn off the ready queue, remove dependencies on the issued insn > > So, given insn1 which feeds insn2 we will never issue insn1 & insn2 in the > same cycle. I noticed this the other day in a different context. Does it seem worthwhile to add some sort of target define to control adding dependant insns to the ready queue in the same cycle? It's true that it doesn't matter to the vast majority of the processors we support, but I'm thinking of VLIW parts that do actually have write-after-read conflicts within a cycle. r~ From mboxrd@z Thu Jan 1 00:00:00 1970 From: Richard Henderson To: law@cygnus.com, Jerry Quinn Cc: egcs@egcs.cygnus.com Subject: Re: Fwd: Questions on PA machine description? Date: Wed, 31 Mar 1999 23:46:00 -0000 Message-ID: <19990319173226.C14722@cygnus.com> References: <36F17F8C.9FD937FA@americasm01.nt.com> <18375.921819620@hurl.cygnus.com> X-SW-Source: 1999-03n/msg00686.html Message-ID: <19990331234600.klf3xuja1Y9sauErs_0ou-Cnnm_FDJWg8yYPs7LaXaI@z> On Thu, Mar 18, 1999 at 10:00:20PM -0700, Jeffrey A Law wrote: > It has a structure like: > > while (not all insns scheduled) > add insns with no outstanding dependencies to the ready queue > sort the ready queue > while (ready list is not empty && target can issue more insns) > issue an insn off the ready queue, remove dependencies on the issued insn > > So, given insn1 which feeds insn2 we will never issue insn1 & insn2 in the > same cycle. I noticed this the other day in a different context. Does it seem worthwhile to add some sort of target define to control adding dependant insns to the ready queue in the same cycle? It's true that it doesn't matter to the vast majority of the processors we support, but I'm thinking of VLIW parts that do actually have write-after-read conflicts within a cycle. r~