Re: Fwd: Questions on PA machine description?

[Jeffrey A Law <law@upchuck.cygnus.com>]

  In message < 36E3E35A.4BB420BE@americasm01.nt.com >you write:
  > > ;; We have two basic ALUs.
  > > (define_function_unit "pa7100LCalu" 2 2
  > >   (and
  > >     (eq_attr "type" "!fpcc,fpalu,fpmulsgl,fpmuldbl,fpdivsgl,fpsqrtsgl,
  > > fpdivdbl,fpsqrtdbl,load,fpload,store,fpstore,shift,nullshift")
  > >    (eq_attr "cpu" "7100LC,7200")) 1 1)
  > > 
  > > It says there are 2 ALU's.  The READY=1 and DELAY=1 appear to me to be a 
  > > gate so that each unit can be issued 1 insn per cycle.
Correct.


  > What is confusing is the SIMULTANEITY of 2.  The documentation claims that
  > this means that each unit can have two active insns issued at a time.  But
  > this isn't true.
Could well be an oversight on my part.  It's been a long time since I wrote
that stuff.


  > > Also, my reading of the definition of SIMULTANEITY seems to indicate
  > > that it should be 1 for the pa7100LCfp_div function unit since the
  > > div/sqrt portion of the FPU can only execute one insn at a time.  Is
  > > this correct or wrong?
I believe this is correct.  The simultaneity should be one.

  > > There is a comment that shifts and memory ops execute in one of the
  > > ALU's but that that can't be modeled.
That was true at one time.  Or more correctly it couldn't be easily modeled.


  > Can someone explain what that means.
Basically one of the ALUs is not complete and can only handle a subset of the
ALU instructions.

So, stuff like adds, subtracts, compares, etc can issue to either ALU, but
a memory load/store or a shift instruction can only issue to the first
alu.  Assuming I remember everything from the LC series correctly.

jeff