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From: Jojo R <rjiejie@linux.alibaba.com>
To: GCC Development <gcc@gcc.gnu.org>
Subject: How to describe ‘earlyclobber’ explicitly for specific source operand ?
Date: Fri, 19 Nov 2021 15:28:02 +0800	[thread overview]
Message-ID: <1b032580-97c7-41c5-9930-9a7354ae4151@Spark> (raw)
In-Reply-To: <eb109969-0133-49eb-b392-b35a065f12ba@Spark>

Hi,

	We know gcc supply earlyclobber function to avoid register overlap,

	but it can not describe explicitly for specific source operand, is it right ?

	The vector ISA spec of risc-v describe some register overlap rules here:

	https://github.com/riscv/riscv-v-spec/blob/master/v-spec.adoc#sec-vec-operands

	e.g.

	# Widening signed integer add/subtract, 2*SEW = 2*SEW +/- SEW
	vwadd.wv vd, vs2, vs1, vm # vector-vector

	it means vd can overlap vs2, but can not overlap vs1,
	there are more registers are wasted if gcc can not describe earlyclobber of vd only for vs1,
	also gcc will generate extra REG-REG move instruction :(

	Any suggestions ?

Thanks.

— Jojo

       reply	other threads:[~2021-11-19  7:28 UTC|newest]

Thread overview: 4+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
     [not found] <eb109969-0133-49eb-b392-b35a065f12ba@Spark>
2021-11-19  7:28 ` Jojo R [this message]
2021-11-19 21:54   ` Peter Bergner
2021-11-22  6:40     ` Jojo R
2021-11-23 12:22       ` Richard Earnshaw

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