From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 31981 invoked by alias); 22 May 2019 06:39:32 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Id: List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 31973 invoked by uid 89); 22 May 2019 06:39:32 -0000 Authentication-Results: sourceware.org; auth=none X-Spam-SWARE-Status: No, score=-1.9 required=5.0 tests=BAYES_00,SPF_PASS autolearn=ham version=3.3.1 spammy=H*r:authenticated, determining, extremely X-HELO: srv-07.MPA-Garching.MPG.DE Received: from srv-07.MPA-Garching.MPG.DE (HELO srv-07.MPA-Garching.MPG.DE) (130.183.82.26) by sourceware.org (qpsmtpd/0.93/v0.84-503-g423c35a) with ESMTP; Wed, 22 May 2019 06:39:29 +0000 Received: from [192.168.178.31] (ppp-62-216-202-233.dynamic.mnet-online.de [62.216.202.233]) (authenticated bits=0) by srv-07.MPA-Garching.MPG.DE (8.15.2/8.15.2) with ESMTPSA id x4M6dQbI045684 (version=TLSv1.3 cipher=TLS_AES_256_GCM_SHA384 bits=256 verify=NO) for ; Wed, 22 May 2019 08:39:26 +0200 From: Martin Reinecke Subject: Determining maximum vector length supported by the CPU? To: gcc@gcc.gnu.org Openpgp: preference=signencrypt Message-ID: <1ceb35b6-4a28-8739-90d4-c300fd81b044@mpa-garching.mpg.de> Date: Wed, 22 May 2019 06:39:00 -0000 User-Agent: Mozilla/5.0 (X11; Linux x86_64; rv:60.0) Gecko/20100101 Thunderbird/60.6.1 MIME-Version: 1.0 Content-Type: text/plain; charset=utf-8 Content-Transfer-Encoding: 7bit X-SW-Source: 2019-05/txt/msg00172.txt.bz2 [Disclaimer: I sent this to gcc-help two weeks ago, but didn't get an answer. Maybe the topic is more suited for the main gcc list ... I really think the feature in question would be extremely useful to have, and easy to add!] Hi, I'm currently writing an FFT library which tries to make use of SIMD instructions and uses a lot of variables with __attribute__ ((vector_size (xyz)) The resulting source is nicely portable and architecture-independent - except for the one place where I need to determine the maximum hardware-supported vector length on the target CPU. This currently looks like #if defined(__AVX__) constexpr int veclen=32; #elif defined(__SSE2__) constexpr int veclen=16; [...] This approach requires me to add an #ifdef for many architectures, most of which I cannot really test on ... and new architectures will be unsupported by default. Hence my question: is there a way in gcc to determine the hardware vector length for the architecture the compiler is currently targeting? Some predefined macro like HARDWARE_VECTOR_LENGTH_IN_BYTES which is 32 for AVX, 16 for SSE2, and has proper values for Neon, VPX etc. etc. If this is not provided at the moment, would it bo possible to add this in the future? This could massively simplify writing and maintaining multi-platform SIMD code. Thanks, Martin