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From: Michael Meissner <meissner@cygnus.com>
To: Mark Mitchell <mark@codesourcery.com>
Cc: amylaar@cygnus.co.uk, geoffk@cygnus.com, gcc@gcc.gnu.org
Subject: Re: ssa bootstrap problem on x86 (cmpstrsi_1 pattern)
Date: Thu, 27 Jul 2000 17:57:00 -0000	[thread overview]
Message-ID: <20000727205727.55452@cse.cygnus.com> (raw)
In-Reply-To: <20000727172208M.mitchell@codesourcery.com>

On Thu, Jul 27, 2000 at 05:22:08PM -0700, Mark Mitchell wrote:
> >>>>> "Joern" == Joern Rennecke <amylaar@cygnus.co.uk> writes:
> 
>     >> The only reason clobbers appear this early in the compiler is
>     >> that GCC generates machine-specific code very early.  There is
>     >> no operation
> 
>     Joern> That is not true.  When gcc synthesizes a move that is
>     Joern> wider than the widest one available in the machine
>     Joern> description, it first clobbers the destination, then does a
>     Joern> series of moves into SUBREGs of the destination.
> 
> But, again, isn't that a machine-specific issue?  These moves could be
> represented directly as a SET and then resolved to an operation
> involving SUBREGs and CLOBBERs later.

Actually what we should do for for all arithmetic operations, including moves,
is issue the generic operation (with no clobbers) in the rtl phase, and then in
the post ssa phase, reissue the operations in a machine dependent manner,
possibly issuing function calls, move by pieces, etc.

Lets say a machine decscription has adddi3 defined as (%L accesses the lower
part of the register), and no movdi instruction:

	(defun "adddi3"
	  [(set (match_operand:DI 0 "register_operand" "=&r")
		(plus:DI (match_operand:DI 1 "register_operand" "%r")
			 (match_operand:DI 2 "register_operand" "r")))
	   (clobber (match_scratch:SI 3 "=&r"))]
	  ""
	  "add %0,%1,%2\;add %L0,%L1,%L2\;sltu %3,%L0,%L1\;add %0,%0,%3")

Thus in rtl you might have:

	(set (reg:DI 123)
	     (plus:DI (reg:DI 124)
		      (const_int 1)))

Then after ssa you might have:

	;; These are the movdi (reg:DI (const_int 1)) done in pieces
	(clobber (reg:DI 456))
	(set (subreg:SI (reg:DI 456) 0)
	     (const_int 0))
	(set (subreg:SI (reg:DI 456) 1)
	     (const_int 1))

	;; This is the rtl generated by the MD's gen_adddi3
	(parallel [(set (reg:DI 123)
			(plus:DI (reg:DI 124)
				 (reg:DI 456)))
		   (clobber (match_scratch:SI))])

Thus you pretend that until after ssa, you have a perfect machine that
implements all opcodes without any restrictions.  I suspect you might need new
rtl for representing arguments, maybe (IN_ARG <num>) and (OUT_ARG <num>).

-- 
Michael Meissner, Red Hat, Inc.
PMB 198, 174 Littleton Road #3, Westford, Massachusetts 01886, USA
Work:	  meissner@redhat.com		phone: +1 978-486-9304
Non-work: meissner@spectacle-pond.org	fax:   +1 978-692-4482

  reply	other threads:[~2000-07-27 17:57 UTC|newest]

Thread overview: 20+ messages / expand[flat|nested]  mbox.gz  Atom feed  top
2000-07-22 21:24 Geoff Keating
2000-07-23  0:50 ` Mark Mitchell
2000-07-24 11:51   ` Geoff Keating
2000-07-25  3:20     ` Richard Earnshaw
2000-07-26 22:55     ` Mark Mitchell
2000-07-27 12:50       ` Geoff Keating
2000-07-27 13:10         ` Mark Mitchell
2000-07-27 14:48           ` Richard Henderson
2000-07-27 15:13             ` Mark Mitchell
2000-07-27 15:14               ` Richard Henderson
2000-07-27 15:28                 ` Mark Mitchell
2000-07-27 15:35                   ` Richard Henderson
2000-07-27 15:42                     ` Mark Mitchell
2000-07-27 15:46               ` Geoff Keating
2000-07-27 15:44           ` Geoff Keating
2000-07-27 16:01             ` Mark Mitchell
2000-07-27 16:59               ` Joern Rennecke
2000-07-27 17:22                 ` Mark Mitchell
2000-07-27 17:57                   ` Michael Meissner [this message]
2000-07-27 18:31                     ` Mark Mitchell

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