Re: A bit of vector extension documentation

[Diego Novillo <dnovillo@redhat.com>]

On Fri, 28 Sep 2001, Toon Moene wrote:

> Diego Novillo wrote:
> 
> > On Fri, 28 Sep 2001, David Edelsohn wrote:
> 
> > >       I thought the point of the paper is that it is a generalization
> > > that does not require loops.  For SIMD, as opposed to vector,
> > > architectures, it might be better because it can take advantage of such
> > > instructions without the loop setup overhead.
> > >
> > Yes, the paper does not attempt to design a vectorizing compiler.
> > It merely points out that in several cases you can get away with
> > converting sequence of expressions into SIMD instructions.  They
> > do have the limitation of working on single basic blocks, though.
> 
> Hmmm, wouldn't that already help on most of the interesting Fortran
> loops, when unrolled (i.e., when "converting sequences of expressions
> into SIMD instructions" is performed after loop unrolling) ?
> 
Oh, most definitely.  It was just an observation of an obvious
extension to their work.  If the analysis is globalized you can
minimize the overhead of packing/unpacking the vector instructions
at block boundaries (if you can re-use a previous packing, for
instance).

The ideas in the paper are certainly interesting and I think
could be put to very good use in GCC.

Diego.