Index: gcc/config/rs6000/rs6000.c
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v
retrieving revision 1.263
diff -u -r1.263 rs6000.c
--- rs6000.c	2001/12/17 16:25:12	1.263
+++ rs6000.c	2001/12/17 18:29:25
@@ -1167,6 +1167,15 @@
   return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode);
 }
 
+/* Return 1 if the operand is 1.0.  */
+int
+one_fp_constant (op, mode)
+     rtx op;
+     enum machine_mode mode;
+{
+  return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST1_RTX (mode);
+}
+
 /* Return 1 if the operand is in volatile memory.  Note that during
    the RTL generation phase, memory_operand does not return TRUE for
    volatile memory references.  So this function allows us to
Index: gcc/config/rs6000/rs6000.h
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v
retrieving revision 1.160
diff -u -r1.160 rs6000.h
--- rs6000.h	2001/12/17 15:05:38	1.160
+++ rs6000.h	2001/12/17 18:29:30
@@ -2804,6 +2804,7 @@
   {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}},			   \
   {"easy_fp_constant", {CONST_DOUBLE}},					   \
   {"zero_fp_constant", {CONST_DOUBLE}},					   \
+  {"one_fp_constant", {CONST_DOUBLE}},					   \
   {"reg_or_mem_operand", {SUBREG, MEM, REG}},				   \
   {"lwa_operand", {SUBREG, MEM, REG}},					   \
   {"volatile_mem_operand", {MEM}},					   \
Index: gcc/config/rs6000/rs6000.md
===================================================================
RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v
retrieving revision 1.147
diff -u -r1.147 rs6000.md
--- rs6000.md	2001/12/14 02:43:26	1.147
+++ rs6000.md	2001/12/17 18:29:38
@@ -37,7 +37,7 @@
 
 ;; Define an insn type attribute.  This is used in function unit delay
 ;; computations.
-(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec"
+(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,srec,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec"
   (const_string "integer"))
 
 ;; Length (in bytes).
@@ -653,6 +653,11 @@
   17 17)
 
 (define_function_unit "fpu" 1 0
+  (and (eq_attr "type" "srec")
+       (eq_attr "cpu" "ppc7400"))
+  10 10)
+
+(define_function_unit "fpu" 1 0
   (and (eq_attr "type" "sdiv")
        (eq_attr "cpu" "ppc7450"))
   21 21)
@@ -4914,6 +4919,14 @@
 		(match_operand:SF 2 "gpc_reg_operand" "")))]
   "TARGET_HARD_FLOAT"
   "")
+
+(define_insn ""
+  [(set (match_operand:SF 0 "gpc_reg_operand" "=f")
+	(div:SF (match_operand:SF 1 "one_fp_constant" "F")
+		(match_operand:SF 2 "gpc_reg_operand" "f")))]
+  "TARGET_POWERPC && TARGET_HARD_FLOAT"
+  "fres %0,%2"
+  [(set_attr "type" "srec")])
 
 (define_insn ""
   [(set (match_operand:SF 0 "gpc_reg_operand" "=f")