From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 5248 invoked by alias); 17 Dec 2001 20:54:42 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 5133 invoked from network); 17 Dec 2001 20:54:37 -0000 Received: from unknown (HELO Nicole.fhm.edu) (213.7.83.91) by sources.redhat.com with SMTP; 17 Dec 2001 20:54:37 -0000 Received: from fhm.edu (unknown [10.23.201.7]) by Nicole.fhm.edu (Postfix on SuSE Linux 7.2 (i386)) with ESMTP id 8F8296EE2; Mon, 17 Dec 2001 21:09:39 +0100 (CET) Date: Mon, 17 Dec 2001 12:54:00 -0000 From: degger@fhm.edu Reply-To: degger@fhm.edu Subject: Patch to add missing PPC instruction To: gcc-patches@gcc.gnu.org Cc: gcc@gcc.gnu.org MIME-Version: 1.0 Content-Type: MULTIPART/mixed; BOUNDARY="-922285545-1804289383-1008615783=:23958" Content-Transfer-Encoding: BINARY Message-Id: <20011217200939.8F8296EE2@Nicole.fhm.edu> X-SW-Source: 2001-12/txt/msg00930.txt.bz2 ---922285545-1804289383-1008615783=:23958 Content-Type: TEXT/plain; charset=us-ascii Content-length: 933 Hija, the attached patch is supposed to add the the fres instruction and necessary computation code to the rs6000 backend. fres is a "floating point single precision reciprocal" mnemonic which is available on at least the 7400 and 7410 (haven't heard back from Dale which other CPUs have it, but they can be added later) which is faster than a single precision divide and spares the storage for the 1.0, a register and the necessary load instructions to get them into memory. This has boostrapped on powerpc-linux-gnu and passed the testsuite without regressions. -- Servus, Daniel 2001-12-17 Daniel Egger * config/rs6000/rs6000.md: Add missing fres mnemonic (floating point single precision reciprocal) to the 7400 definition and emit it. * config/rs6000/rs6000.c (one_fp_constant): Add helper function to check for a float 1.0 constant... * config/rs6000/rs6000.h: ... and declare it here. ---922285545-1804289383-1008615783=:23958 Content-Type: TEXT/plain; name="rs6000.diff" Content-Disposition: attachment; filename="rs6000.diff" Content-length: 3090 Index: gcc/config/rs6000/rs6000.c =================================================================== RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.c,v retrieving revision 1.263 diff -u -r1.263 rs6000.c --- rs6000.c 2001/12/17 16:25:12 1.263 +++ rs6000.c 2001/12/17 18:29:25 @@ -1167,6 +1167,15 @@ return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST0_RTX (mode); } +/* Return 1 if the operand is 1.0. */ +int +one_fp_constant (op, mode) + rtx op; + enum machine_mode mode; +{ + return GET_MODE_CLASS (mode) == MODE_FLOAT && op == CONST1_RTX (mode); +} + /* Return 1 if the operand is in volatile memory. Note that during the RTL generation phase, memory_operand does not return TRUE for volatile memory references. So this function allows us to Index: gcc/config/rs6000/rs6000.h =================================================================== RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.h,v retrieving revision 1.160 diff -u -r1.160 rs6000.h --- rs6000.h 2001/12/17 15:05:38 1.160 +++ rs6000.h 2001/12/17 18:29:30 @@ -2804,6 +2804,7 @@ {"got_no_const_operand", {SYMBOL_REF, LABEL_REF}}, \ {"easy_fp_constant", {CONST_DOUBLE}}, \ {"zero_fp_constant", {CONST_DOUBLE}}, \ + {"one_fp_constant", {CONST_DOUBLE}}, \ {"reg_or_mem_operand", {SUBREG, MEM, REG}}, \ {"lwa_operand", {SUBREG, MEM, REG}}, \ {"volatile_mem_operand", {MEM}}, \ Index: gcc/config/rs6000/rs6000.md =================================================================== RCS file: /cvs/gcc/gcc/gcc/config/rs6000/rs6000.md,v retrieving revision 1.147 diff -u -r1.147 rs6000.md --- rs6000.md 2001/12/14 02:43:26 1.147 +++ rs6000.md 2001/12/17 18:29:38 @@ -37,7 +37,7 @@ ;; Define an insn type attribute. This is used in function unit delay ;; computations. -(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" +(define_attr "type" "integer,load,store,fpload,fpstore,vecload,vecstore,imul,imul2,imul3,lmul,idiv,ldiv,branch,compare,cr_logical,delayed_compare,fpcompare,mtjmpr,fp,dmul,srec,sdiv,ddiv,ssqrt,dsqrt,jmpreg,vecsimple,veccomplex,veccmp,vecperm,vecfloat,altivec" (const_string "integer")) ;; Length (in bytes). @@ -653,6 +653,11 @@ 17 17) (define_function_unit "fpu" 1 0 + (and (eq_attr "type" "srec") + (eq_attr "cpu" "ppc7400")) + 10 10) + +(define_function_unit "fpu" 1 0 (and (eq_attr "type" "sdiv") (eq_attr "cpu" "ppc7450")) 21 21) @@ -4914,6 +4919,14 @@ (match_operand:SF 2 "gpc_reg_operand" "")))] "TARGET_HARD_FLOAT" "") + +(define_insn "" + [(set (match_operand:SF 0 "gpc_reg_operand" "=f") + (div:SF (match_operand:SF 1 "one_fp_constant" "F") + (match_operand:SF 2 "gpc_reg_operand" "f")))] + "TARGET_POWERPC && TARGET_HARD_FLOAT" + "fres %0,%2" + [(set_attr "type" "srec")]) (define_insn "" [(set (match_operand:SF 0 "gpc_reg_operand" "=f") ---922285545-1804289383-1008615783=:23958--