From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 4612 invoked by alias); 29 Jan 2002 13:13:06 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 4464 invoked from network); 29 Jan 2002 13:12:57 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 29 Jan 2002 13:12:57 -0000 Received: by fw-cam.cambridge.arm.com; id NAA21689; Tue, 29 Jan 2002 13:12:56 GMT Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma021007; Tue, 29 Jan 02 13:12:17 GMT Received: from cam-mail2.cambridge.arm.com (localhost [127.0.0.1]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id NAA14460; Tue, 29 Jan 2002 13:12:16 GMT Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id NAA13850; Tue, 29 Jan 2002 13:12:16 GMT Message-Id: <200201291312.NAA13850@cam-mail2.cambridge.arm.com> X-Mailer: exmh version 2.0.2 2/24/98 To: Jim Wilson cc: law@redhat.com, gcc@gcc.gnu.org, Richard.Earnshaw@arm.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: paradoxical subreg problem In-reply-to: Your message of "Mon, 28 Jan 2002 13:47:26 PST." <200201282147.NAA19688@rtl.cygnus.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Tue, 29 Jan 2002 10:55:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-01/txt/msg01877.txt.bz2 > In article <16350.1012242676@porcupine.cygnus.com> you write: > >Think very very carefully about the semantics of a paradoxical subreg. > > A paradoxical subreg can have one of two different meanings, depending on > context. > > 1) The extra bits are don't care bits. This usage can occur anywhere, and > is primarily used when manipulating values larger than the word size. > This perhaps requires that the operand be a register, but I'm not sure. > For instance, on a 32-bit target, given (subreg:DI (reg:SI 100)), the > extra 32-bits are don't care bits. > 2) The extra bits are known to be zero or one, depending on whether loads > zero or sign extend by default. This is only used for values smaller than > or equal to the the word size, and I think this also requires that the > operand be a MEM, but I'm not positive about the last condition. For > instance, on a 32-bit target with zero-extending loads, given > (subreg:SI (mem:QI ...)), the extra 24-bits are known to be zero. This > usage occurs only between combine and reload. > > It has been this way for over a decade I'd say. > > The first meaning came first, and has obvious uses. I believe the second > meaning arose because of our primarily CISC oriented view at the time. > Since predicates know about subregs already, using subregs for zero/sign > extended loads means that they would be accepted automatically. If we > added the explicit zero/sign extension operators, then a lot of predicates > and patterns would have to be modified to allow zero/sign extension operators. > Nowadays, the prevailing wisdom is that you should never create an insn > that will require a reload, and thus it may be that the second type of > paradoxical subreg is no longer useful. We already have the problem that > combine.c and recog.c have special code checking INSN_SCHEDULING to get rid > of the second class of paradoxical subregs. This code is unclean though, > as we never should have created these paradoxical subregs on a load/store > (RISC) machine to begin with. If the patterns in the md file don't allow > MEM, then recog should not be accepting (subreg (mem)) as a register operand. > > There might be a second justification that this feature allows for better > optimization, by exposing zero/sign extensions that would otherwise be > hidden. However, I don't think this is convincing. Combine has code to > keep track of sign-bit copies now, and we can do this just as well by using > explicit zero_extend/sign_extend operators instead of using subregs. Yep, that summarizes my understanding as well. Most of this rubbish seems to come about because register_operand accepts subreg(mem) as a valid register. This has always seemed daft to me, and indeed the arm back-end hardly ever uses register_operand because of this (it seems to generate worse code by forcing spills during reload that would otherwise have been caught during general register allocation). R.