From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 27311 invoked by alias); 31 Jan 2002 12:04:01 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 27213 invoked from network); 31 Jan 2002 12:03:56 -0000 Received: from unknown (HELO fw-cam.cambridge.arm.com) (193.131.176.3) by sources.redhat.com with SMTP; 31 Jan 2002 12:03:56 -0000 Received: by fw-cam.cambridge.arm.com; id MAA27024; Thu, 31 Jan 2002 12:03:54 GMT Received: from unknown(172.16.1.2) by fw-cam.cambridge.arm.com via smap (V5.5) id xma026451; Thu, 31 Jan 02 12:03:22 GMT Received: from cam-mail2.cambridge.arm.com (localhost [127.0.0.1]) by cam-admin0.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id MAA20349; Thu, 31 Jan 2002 12:03:21 GMT Received: from sun18.cambridge.arm.com (sun18.cambridge.arm.com [172.16.2.18]) by cam-mail2.cambridge.arm.com (8.9.3/8.9.3) with ESMTP id MAA06105; Thu, 31 Jan 2002 12:03:21 GMT Message-Id: <200201311203.MAA06105@cam-mail2.cambridge.arm.com> X-Mailer: exmh version 2.0.2 2/24/98 To: Greg McGary cc: law@redhat.com, gcc@gcc.gnu.org, Richard.Earnshaw@arm.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: condition codes, haifa-sched and virtual-stack-vars In-reply-to: Your message of "30 Jan 2002 12:54:58 MST." Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Thu, 31 Jan 2002 07:49:00 -0000 From: Richard Earnshaw X-SW-Source: 2002-01/txt/msg01981.txt.bz2 If most insns clobber the condition code register, then trying to represent it at all to the compiler isn't very helpful. GCC relies on being able to generate some types of insn without going through the expanders (simple moves for instance), so you might end up with spurious aborts if your normal move/addition/subtraction patterns require a clobber. You don't have to use the CC0 approach however, it is possible to create a description of a machine that has no condition code register at all, and conditional branches (about the only time that conditions are really needed within the compiler) can be represented as compare-and-branch instructions. See the TARGET_THUMB instructions of the ARM machine description for an example. R.