heads up, upcoming ppc variant (e500, booke32)

heads up, upcoming ppc variant (e500, booke32)

[Aldy Hernandez]

hi guys.

just an fyi, over the next week i'll be contributing the e500 port, a
32-bit booke implementation.

i'm not sure if the specs are available publicly yet.  a quick search in
google returns:

    http://www.motorola.com/mediacenter/news/detail/0,1958,568_322_23,00.html

the chip is a powerpc implementation (though david disagrees :) because of
a few quirks as rewards to floating point).  so, it'll be part of
config/rs6000/.

here's the skinny:

- gprs have an upper 32-bits only available for SIMD operations.  so
  gprs are 64-bits, but scalar operations still see 32-bits.

- the chip can do single precision floating point operations... in the
  gprs.  so it has no FPRS.

- simd types are: V2SI, V2SF, V4HI

- there's an <spe.h> that's not nearly as bad as <altivec.h> :-)

nothing out of the ordinary, except there are some issues with exception
handling that'll have to be discussed separately.  basically, dwarf2
has no way of representing register size when saving GPRs.  our current
unwinder assumes gprs are saved and restored in:

  typedef unsigned _Unwind_Word __attribute__((__mode__(__word__)));

which may not necessarily true for the e500, since we save some gprs in
64-bits, though the architecture is still 32-bit.  sigh...  i'll bring this
up later.

and there are of course, the perfunctory ppc cleanups along the way :).

cheerios.

aldy