Re: ICE building glibc-2.2.5 using m68k-linux gcc-3.1

[Richard Zidlicky <Richard.Zidlicky@stud.informatik.uni-erlangen.de>]

On Thu, Jul 25, 2002 at 06:04:31PM -0700, Richard Henderson wrote:
> On Thu, Jul 25, 2002 at 03:33:20PM -0400, Peter Barada wrote:
> > (gdb) call debug_rtx(set)
> > 
> > (set (strict_low_part (reg:HI 6 %d6))
> >     (reg:HI 30))
> 
> This is wrong.  The argument to STRICT_LOW_PART must always be
> a SUBREG of a REG.

I have tracked it down to following kludge which makes gen_lowpart
return a REG instead of SUBREG ins some cases:

simplify-rtx.c:simplify_subreg:2644
      int final_regno = subreg_hard_regno (gen_rtx_SUBREG (outermode, op, byte),
					   0);

      /* ??? We do allow it if the current REG is not valid for
	 its mode.  This is a kludge to work around how float/complex
	 arguments are passed on 32-bit Sparc and should be fixed.  */
      if (HARD_REGNO_MODE_OK (final_regno, outermode)
	  || ! HARD_REGNO_MODE_OK (REGNO (op), innermode))
	{
	  rtx x = gen_rtx_REG (outermode, final_regno);

	  /* Propagate original regno.  We don't have any way to specify
	     the offset inside orignal regno, so do so only for lowpart.
	     The information is used only by alias analysis that can not
	     grog partial register anyway.  */

	  if (subreg_lowpart_offset (outermode, innermode) == byte)
	    ORIGINAL_REGNO (x) = ORIGINAL_REGNO (op);
	  return x;
	}

This returns REG instead of SUBREG, is this special case still needed?

The backtrace at this point is:
#0  simplify_subreg (outermode=HImode, op=0x400dbd10, innermode=SImode, byte=2)
    at ../../gcc-3.1/gcc/simplify-rtx.c:2653
#1  0x81597c2 in simplify_gen_subreg (outermode=HImode, op=0x400dbd10, 
    innermode=SImode, byte=2) at ../../gcc-3.1/gcc/simplify-rtx.c:2724
#2  0x80b2977 in gen_lowpart_common (mode=HImode, x=0x400dbd10)
    at ../../gcc-3.1/gcc/emit-rtl.c:857
#3  0x80b2cf2 in gen_lowpart (mode=HImode, x=0x400dbd10)
    at ../../gcc-3.1/gcc/emit-rtl.c:1153
#4  0x80f9dc3 in gen_zero_extendhisi2 (operand0=0x400dbd10, 
    operand1=0x400dbdc0) at insn-emit.c:2952
#5  0x8118e4a in emit_unop_insn (icode=454, target=0x400dbd10, op0=0x400dbdc0, 
    code=ZERO_EXTEND) at ../../gcc-3.1/gcc/optabs.c:2682




Richard