From: Daniel Jacobowitz <drow@false.org>
To: Daniel Berlin <dberlin@dberlin.org>
Cc: gcc@gcc.gnu.org
Subject: Re: Reasonable L1 cache miss rate for gcc
Date: Sun, 11 Aug 2002 08:20:00 -0000 [thread overview]
Message-ID: <20020811152045.GA3379@nevyn.them.org> (raw)
In-Reply-To: <Pine.LNX.4.44.0208110037020.4997-100000@dberlin.org>
On Sun, Aug 11, 2002 at 01:12:39AM -0400, Daniel Berlin wrote:
> What is a reasonable L1 cache miss rate (for memory loads
> only not instructions) is for a P4 running GCC?
>
> I have the exact figures, but without some idea of what reasonable would
> be, i have no idea how *bad* it is.
>
> Percentage wise, it's a 14-25% miss rate (depending on input).
>
> Of course, I really want to know about L2's, but the file describing all
> the available p4 pmcs says:
> Sigh.
>
> Someone with a PIII should be able to get oprofile to give us some l2
> numbers.
Assuming that I actually figured out what these numbers mean...
I remade insn-*.o in a gcc HEAD build with two compilers (no
optimization):
DATA_MEM_REFS L2_LINES_IN L2 Miss %
GCC 2.95.3 cc1 4.32e9 3.23e7 0.7%
GCC 3.1.1 cc1 7.0265e9 6.3e7 0.8%
Something tells me I've got the wrong numbers, though... those look far
too low. If someone cares to enlighten me on the right counters to
use, I'll be more thorough.
--
Daniel Jacobowitz
MontaVista Software Debian GNU/Linux Developer
next prev parent reply other threads:[~2002-08-11 8:20 UTC|newest]
Thread overview: 3+ messages / expand[flat|nested] mbox.gz Atom feed top
2002-08-10 22:12 Daniel Berlin
2002-08-11 8:20 ` Daniel Jacobowitz [this message]
2002-08-11 9:02 ` Daniel Berlin
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