Reasonable L1 cache miss rate for gcc

Reasonable L1 cache miss rate for gcc

[Daniel Berlin]

What is a reasonable L1 cache miss rate (for memory loads 
only not instructions) is for a P4 running GCC?

I have the exact figures, but without some idea of what reasonable would 
be, i have no idea how *bad* it is.

Percentage wise, it's a 14-25% miss rate (depending on input).

Of course, I really want to know about L2's, but the file describing all  
the available p4 pmcs says:


    <!-- I have not been able to get counts that make sense from ld_miss_2L_retired yet. -->
    <ld_miss_2L_retired>
        <type>replay</type>
        <tag_setup>
            <pebs_enable>
                <set>
                    <l1miss/>
                    <tag/>
                </set>
            </pebs_enable>
            <pebs_matrix_vert>
                <set>
                    <ld/>
                </set>
            </pebs_matrix_vert>
        </tag_setup>
        <count_setup>
            <replay_event>
                <set><nbogus/></set>
            </replay_event>
        </count_setup>
    </ld_miss_2L_retired>


I agree with the conclusion of the comment, the l2 miss numbers it 
gives don't make sense.

Sigh.

Someone with a PIII should be able to get oprofile to give us some l2 
numbers.

On the other hand, those using cachegrind should be aware that it took a 
*long* time for cachegrind cc1 run on the same input (preprocessed 
version of expr.c at -O2), and the numbers it came up with are off by a 
factor of 7 (on the low side.  IE it claims 2 when it's really 14).

So i'm not too keen on using cachegrind numbers to model our cache 
behavior.

--Dan

Re: Reasonable L1 cache miss rate for gcc

[Daniel Jacobowitz]

On Sun, Aug 11, 2002 at 01:12:39AM -0400, Daniel Berlin wrote:
> What is a reasonable L1 cache miss rate (for memory loads 
> only not instructions) is for a P4 running GCC?
> 
> I have the exact figures, but without some idea of what reasonable would 
> be, i have no idea how *bad* it is.
> 
> Percentage wise, it's a 14-25% miss rate (depending on input).
> 
> Of course, I really want to know about L2's, but the file describing all  
> the available p4 pmcs says:

> Sigh.
> 
> Someone with a PIII should be able to get oprofile to give us some l2 
> numbers.

Assuming that I actually figured out what these numbers mean...
I remade insn-*.o in a gcc HEAD build with two compilers (no
optimization):

		DATA_MEM_REFS		L2_LINES_IN	  L2 Miss %
GCC 2.95.3 cc1	 4.32e9			  3.23e7	  0.7%
GCC 3.1.1 cc1	 7.0265e9		  6.3e7		  0.8%

Something tells me I've got the wrong numbers, though... those look far
too low.  If someone cares to enlighten me on the right counters to
use, I'll be more thorough.

-- 
Daniel Jacobowitz
MontaVista Software                         Debian GNU/Linux Developer

Re: Reasonable L1 cache miss rate for gcc

[Daniel Berlin]

On Sun, 11 Aug 2002, Daniel Jacobowitz wrote:

> On Sun, Aug 11, 2002 at 01:12:39AM -0400, Daniel Berlin wrote:
> > What is a reasonable L1 cache miss rate (for memory loads 
> > only not instructions) is for a P4 running GCC?
> > 
> > I have the exact figures, but without some idea of what reasonable would 
> > be, i have no idea how *bad* it is.
> > 
> > Percentage wise, it's a 14-25% miss rate (depending on input).
> > 
> > Of course, I really want to know about L2's, but the file describing all  
> > the available p4 pmcs says:
> 
> > Sigh.
> > 
> > Someone with a PIII should be able to get oprofile to give us some l2 
> > numbers.
> 
> Assuming that I actually figured out what these numbers mean...
> I remade insn-*.o in a gcc HEAD build with two compilers (no
> optimization):
> 
> 		DATA_MEM_REFS		L2_LINES_IN	  L2 Miss %
> GCC 2.95.3 cc1	 4.32e9			  3.23e7	  0.7%
> GCC 3.1.1 cc1	 7.0265e9		  6.3e7		  0.8%
> 
> Something tells me I've got the wrong numbers, though... those look far
> too low.  If someone cares to enlighten me on the right counters to
> use, I'll be more thorough.

Make sure it compiles with optimization on.

But, otherwise, it's quite possible those aren't too low.
Remember it can only take an L2 miss when it misses L1.
So comparing complete data refs to L2 misses will always give you very 
low numbers.