From mboxrd@z Thu Jan  1 00:00:00 1970
Return-Path: <gcc-return-60530-listarch-gcc=gcc.gnu.org@gcc.gnu.org>
Received: (qmail 29061 invoked by alias); 26 Sep 2002 10:25:53 -0000
Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm
Precedence: bulk
List-Archive: <http://gcc.gnu.org/ml/gcc/>
List-Post: <mailto:gcc@gcc.gnu.org>
List-Help: <http://gcc.gnu.org/ml/>
Sender: gcc-owner@gcc.gnu.org
Received: (qmail 29048 invoked from network); 26 Sep 2002 10:25:50 -0000
Received: from unknown (HELO pizda.ninka.net) (216.101.162.242)
  by sources.redhat.com with SMTP; 26 Sep 2002 10:25:50 -0000
Received: from localhost (IDENT:davem@localhost.localdomain [127.0.0.1])
	by pizda.ninka.net (8.9.3/8.9.3) with ESMTP id DAA05321;
	Thu, 26 Sep 2002 03:19:38 -0700
Date: Thu, 26 Sep 2002 03:32:00 -0000
Message-Id: <20020926.031937.45874387.davem@redhat.com>
To: mark@codesourcery.com
Cc: gcc@gcc.gnu.org, gcc-patches@gcc.gnu.org
Subject: Re: Release schedule
From: "David S. Miller" <davem@redhat.com>
In-Reply-To: <20020925.130854.01705734.davem@redhat.com>
References: <23100000.1032978530@warlock.codesourcery.com>
	<20020925.130854.01705734.davem@redhat.com>
Mime-Version: 1.0
Content-Type: Text/Plain; charset=us-ascii
Content-Transfer-Encoding: 7bit
X-SW-Source: 2002-09/txt/msg01040.txt.bz2

   From: "David S. Miller" <davem@redhat.com>
   Date: Wed, 25 Sep 2002 13:08:54 -0700 (PDT)

   target/7842 is a very fundamental flaw in the sparc backend,...

This turned out the be simple to fix once I dug more deeply.
I've installed the fix and will be closing this bug shortly.

32-bit "sll" does not extend like shift right does, although
this is a peculiar behavior it is actually specified this way
in Sparc V9 and indeed how the cpu acts :-)

Checked into mainline and 3.2 branch.

2002-09-25  David S. Miller  <davem@redhat.com>

	PR target/7842
	* config/sparc/sparc.c (set_extends): SImode ASHIFT does not
	extend.

--- ./config/sparc/sparc.c.~1~	Sat May 25 19:42:21 2002
+++ ./config/sparc/sparc.c	Wed Sep 25 21:14:02 2002
@@ -8650,7 +8650,6 @@ set_extends (insn)
 	  return INTVAL (op1) >= 0;
 	return (GET_CODE (op1) == REG && sparc_check_64 (op1, insn) == 1);
       }
-    case ASHIFT:
     case LSHIFTRT:
       return GET_MODE (SET_SRC (pat)) == SImode;
       /* Positive integers leave the high bits zero.  */