load multiple from const labels?

load multiple from const labels?

[N V Krishna]

Hi,
	On inspecting different codes, I see that there are quite a few
loads from constant labels.
e.g.

        ldr     r1, .L224
	ldr     r2, .L224+4

I was wondering if we can use LDM (load multiple) type of instruction on
ARM type of processors here?

I tried inserting LDM instruction as I insert LDM with registers, but gcc
cribbed saying 'internal error--unrecognizable insn:'

I tried inserting one SET instruction and followed by LDM, and this time
gcc cribbed for the SET instruction. Please forgive my ignorance and let
me know if it is not possible to write have instructions like 

mov r1, .L224+immediate 

or I am making some mistake in building the rtl??

Warm regards
Krishna
-- 
Homepage:http://www.cs.purdue.edu/homes/nvk

Re: load multiple from const labels?

[Richard Earnshaw]

> Hi,
> 	On inspecting different codes, I see that there are quite a few
> loads from constant labels.
> e.g.
> 
>         ldr     r1, .L224
> 	ldr     r2, .L224+4
> 
> I was wondering if we can use LDM (load multiple) type of instruction on
> ARM type of processors here?

On processors after ARM 7 it's going to be a loose to make that change, 
the sequence isn't shorter and it generally ends up taking more cycles to 
execute; in addition, the range of an ADR instruction is generally less 
than for LDR, so we end up with more constant pools.  For three or more 
LDR's the balance starts to shift back in favour of using LDM, but even 
then it's not clear that this would be worth the complexity, loss of 
scheduling freedom.

Generating LDM instructions in RTL prior to register allocation is nearly 
impossible unless you keep the use of the values strictly with the load or 
use explicit hard register numbers, since the register allocator has no 
concept of an order of registers within a register class.

R.