From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 12885 invoked by alias); 7 Jan 2003 11:51:06 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 12878 invoked from network); 7 Jan 2003 11:51:04 -0000 Received: from unknown (HELO nile.gnat.com) (205.232.38.5) by 209.249.29.67 with SMTP; 7 Jan 2003 11:51:04 -0000 Received: by nile.gnat.com (Postfix, from userid 338) id 04121F28F4; Tue, 7 Jan 2003 06:50:52 -0500 (EST) To: dewar@gnat.com, ja_walker@earthlink.net, lord@emf.net, mszick@goquest.com Subject: Re: An unusual Performance approach using Synthetic registers Cc: gcc@gcc.gnu.org Message-Id: <20030107115052.04121F28F4@nile.gnat.com> Date: Tue, 07 Jan 2003 12:08:00 -0000 From: dewar@gnat.com (Robert Dewar) X-SW-Source: 2003-01/txt/msg00342.txt.bz2 > I am pretty familiar with the x86 instruction set, but I clearly recall that > I have never seen anything like this. Is there such a thing in the x86 > instruction set, and if so, what is it called? Is it perhaps one of the > testing instructions? There is no prefetch instruction as such on the x86, but of course any access acts as a prefetch in practice.