From: Richard Earnshaw <rearnsha@arm.com>
To: Nick Clifton <nickc@redhat.com>
Cc: Eric de Jong <eric2work@yahoo.com>,
gcc@gnu.org, ericdejong@gmx.net, Richard.Earnshaw@arm.com
Subject: Re: ARM interrupts
Date: Thu, 23 Jan 2003 18:30:00 -0000 [thread overview]
Message-ID: <200301231218.h0NCIXs04000@pc960.cambridge.arm.com> (raw)
In-Reply-To: Your message of "Thu, 23 Jan 2003 11:11:04 GMT." <200301231111.h0NBB7h28534@pc960.cambridge.arm.com>
> #ifdef ATPCS_STACK_ALIGN
> bic sp, sp, #7 /* If stack alignment required. */
> #endif
Thinking about this some more, this isn't needed with the current level of
IRQ support that we provide. We don't allow nested interrupts (we don't
preserve the SPSR), so we can assume that the appropriate interrupt stack
is correctly aligned on entry. At most we need to add a normal stack
adjustment.
R.
next prev parent reply other threads:[~2003-01-23 12:30 UTC|newest]
Thread overview: 7+ messages / expand[flat|nested] mbox.gz Atom feed top
2003-01-22 18:22 Eric de Jong
2003-01-22 18:46 ` Richard Earnshaw
2003-01-23 18:08 ` Nick Clifton
2003-01-23 18:25 ` Richard Earnshaw
2003-01-23 18:30 ` Richard Earnshaw [this message]
2003-01-26 20:28 ` Nick Clifton
2003-01-26 20:31 ` Nick Clifton
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