Re: Strange conditional jumps on the POWER4

[David Edelsohn <dje@watson.ibm.com>]

>>>>> Roger Sayle writes:

Roger> So it looks as though the problem is not a register stall, or scheduling
Roger> problem but with branch prediction and basic block re-ordering.  If
Roger> you're lucky and the compiler gets the branch probabilities right,
Roger> and you always branch the same way it can be done in 300 ticks.  If
Roger> you're unlucky, the compiler gets the probabilities wrong and you
Roger> alternate taken/not-taken it takes 1200 ticks.

	Newer PowerPC processors switched to using a different encoding of
branch hints.  GCC for AIX currently does not enable the assembler mode to
map the mnemonics to the new hint bits, so Power4 always uses its internal
branch prediction, even if the +/- is present.  The Power4 processor is
predicting the branch correctly.

	I suspect the problem is the branch to branch.  Power4 has a one
cycle latency between branches.  In the faster code, the conditional
branch is not taken, we overwrite the register (hidden by renaming) and we
fallthru to the branch on counter.  For the slower code, we don't
overwrite the regiser, but the conditional branch is taken jumping to the
branch on counter.  The branch on counter is held off one cycle, leading
to the performance degradation.

David