Re: gcc and the IA64 ABI

[Richard Henderson <rth@redhat.com>]

On Fri, May 23, 2003 at 11:04:27AM -0700, Winalski, Paul wrote:
> The part of the IA64 ABI under discussion restricts tail calls to undefined
> external symbols to those cases where the compiler knows that the
> target of the tail call will be in the same component (and hence share
> the same gp value) as the routine making the tail call.

Yes.

Though we missed this restriction in GCC.  So at present GCC does
not follow this bit of the ABI, and doesn't preserve *any* value
in the GP after a call.

But I suspect you know this and that's why you're writing this mail.  ;-)

> Our study of the situation so far indicates that tail call opportunities
> on Itanium are quite limited.  Use of the alloc instruction in the caller
> precludes tail calls, for example.

This is false.  All that is required is that there be another
alloc instruction preceeding the actual jump that deallocates
the caller's register stack frame.

For instance, 

	void foo() { bar(baz()); }

foo:
        .prologue 12, 34
        .mii
        .save ar.pfs, r35
        alloc r35 = ar.pfs, 1, 3, 0, 0
        .save rp, r34
        mov r34 = b0
        mov r33 = r1
        .body
        ;;
        .bbb
        nop 0
        nop 0
        br.call.sptk.many b0 = baz#
        ;;
        .mmi
        mov r32 = r8
        mov r1 = r33
        mov ar.pfs = r35
        .mii
        nop 0
        mov b0 = r34
        ;;
        nop 0
        .mfb
        alloc r2 = ar.pfs, 0, 0, 1, 0
        nop 0
        br.sptk.many bar#
        ;;
        break.f 0
        ;;

> But eliminating caller gp save/restore
> seems to be promising.  Early testing seems to indicate significant
> improvement on some important programs; we're still in the process of
> collecting performance data.

I wouldn't have suspected that this would produce that much of a win,
given that restoring the gp is so cheap; just a single mov instruction.

> If you have evidence that tail call optimization is a significant
> performance win on Itanium, we'd love to hear about it before we
> go charging down the wrong path.

I have no hard data, but I would think that the more tail calls we
can allow, the shallower the register stack depth is needed, and so 
result in less traffic by the RSE.


r~