From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 23722 invoked by alias); 21 Jan 2004 11:57:52 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 23707 invoked from network); 21 Jan 2004 11:57:50 -0000 Received: from unknown (HELO cam-admin0.cambridge.arm.com) (193.131.176.58) by sources.redhat.com with SMTP; 21 Jan 2004 11:57:50 -0000 Received: from pc960.cambridge.arm.com (pc960.cambridge.arm.com [10.1.205.4]) by cam-admin0.cambridge.arm.com (8.12.10/8.12.10) with ESMTP id i0LBveAO007810; Wed, 21 Jan 2004 11:57:40 GMT Received: from pc960.cambridge.arm.com (rearnsha@localhost) by pc960.cambridge.arm.com (8.11.6/8.9.3) with ESMTP id i0LBveM04894; Wed, 21 Jan 2004 11:57:40 GMT Message-Id: <200401211157.i0LBveM04894@pc960.cambridge.arm.com> X-Authentication-Warning: pc960.cambridge.arm.com: rearnsha owned process doing -bs To: Geoffrey Keating cc: Alexandre Oliva , Scott Robert Ladd , Robert Dewar , gcc@gcc.gnu.org, Nick Burrett , Eric Botcazou , Gabriel Dos Reis , Marc Espie , Richard.Earnshaw@arm.com Reply-To: Richard.Earnshaw@arm.com Organization: ARM Ltd. X-Telephone: +44 1223 400569 (direct+voicemail), +44 1223 400400 (switchbd) X-Fax: +44 1223 400410 X-Address: ARM Ltd., 110 Fulbourn Road, Cherry Hinton, Cambridge CB1 9NJ. X-Url: http://www.arm.com/ Subject: Re: gcc 3.5 integration branch proposal In-reply-to: Your message of "Tue, 20 Jan 2004 14:30:04 PST." <31870CEE-4B98-11D8-83EB-000A95B1F520@apple.com> Mime-Version: 1.0 Content-Type: text/plain; charset=us-ascii Date: Wed, 21 Jan 2004 12:12:00 -0000 From: Richard Earnshaw X-SW-Source: 2004-01/txt/msg01639.txt.bz2 > > Typically, on older, slower machines (eg. the mentioned 300Mhz > StrongARM), memory accesses are relatively cheap relative to > computation. Thus, on newer machines it's useful to perform some > computation if this results in smaller final data structures, but this > is not true on older machines. > But on the other hand, caches were smaller, not backed by L2, and were often allocate-on-write only (so zeroing a structure can be very expensive, especially if it is then re-initialized with other data). All of these affect general approaches to what needs optimizing. R.