* Reloading does not proper work on my new 8 bit target, please help
@ 2004-03-16 14:22 ildar
2004-03-16 17:12 ` Joern Rennecke
0 siblings, 1 reply; 6+ messages in thread
From: ildar @ 2004-03-16 14:22 UTC (permalink / raw)
To: gcc
Hello!
I make the port of GCC 3.3.2 on new target 8-bit CPU of Harward
architecture. This CPU has two data pointer register to access to the data
memory. There are no offset address mode and direct address mode. There is
only indirect address mode.
I determine several register classes;
DATA_POINTER_REGS - is BASE_REG_CLASS. The class DATA_POINTER_REGS
contains two classes: POINTER_DP1 and POINTER_DP2;
NO_SYSTEM_REGS - class is specified to describe operands in assembler
commands. NO_SYSTEM_REGS contains GENERAL_REGS, GENERAL_OR_IO_REGS,
DATA_POINTER_REGS,
SYSTEM_REGS - class is specified to describe special registers for CPU
control.
There are the register class initializeres
enum reg_class {
NO_REGS,
R0_REG, /* a0 */
GENERAL_REGS, /* a0..a7 bo..b7 */
GENERAL_OR_IO_REGS, /* c0..c7 */
POINTER_DP1, /* dp1l dp1h */
POINTER_DP2, /* dp2l dp2h */
DATA_IDX_SP_REG, /* i(sp) */
DATA_REGS, /* (dp1) (dp2) */
WINDOWS_REGS, /* wa wb wc */
STACK_POINTER_REGS, /* spl sph */
INDX_REGS, /* idxl idxh */
DATA_PAGE_REGS, /* dp1pg dp2pg */
HIGH_BYTE_MUL_REG, /* mrh */
LOOP_COUNTER_REG, /* lc */
MODES_CONTROL_REGS, /* dpmode,wcmode*/
DATA_POINTER_REGS, /* dp1l,dp1h,dp2l,dp2h */
NO_SYSTEM_REGS, /* a0..a7 bo..b7 c0..c7 dp1 dp2 (dp1) (dp2) i(sp)*/
SYSTEM_REGS, /* (wa wb wc spl sph idxl idxh dp1pg dp2pg mrh lc)*/
ALL_REGS, LIM_REG_CLASSES
};
#define REG_CLASS_NAMES { \
"NO_REGS", \
"R0_REG", /* b0 */ \
"GENERAL_REGS", /* a0..a7 bo..b7 */ \
"GENERAL_OR_IO_REGS", /* c0..c7 */ \
"POINTER_DP1", /* dp1l dp1h */ \
"POINTER_DP2", /* dp2l dp2h */ \
"DATA_IDX_SP_REG", /* i(sp) */ \
"DATA_REGS", /* (dp1) (dp2) */ \
"WINDOWS_REGS", /* wa wb wc */ \
"STACK_POINTER_REGS", /* spl sph */ \
"INDX_REGS", /* idxl idxh */ \
"DATA_PAGE_REGS", /* dp1pg dp2pg */ \
"HIGH_BYTE_MUL_REG", /* mrh */ \
"LOOP_COUNTER_REG", /* lc */ \
"MODES_CONTROL_REGS", /* dpmode,wcmode */ \
"DATA_POINTER_REGS", /* dp1l,dp1h,dp2l,dp2h*/ \
"NO_SYSTEM_REGS", /* a0..a7 bo..b7 c0..c7 dp1 dp2 (dp1) (dp2)
i(sp)*/ \
"SYSTEM_REGS", /* wa wb wc spl sph idxl idxh dp1pg dp2pg mrh lc
*/ \
"ALL_REGS" }
#define REG_CLASS_CONTENTS { \
{0x00000000,0x00000000}, /* "NO_REGS", */ \
{0x00000100,0x00000000}, /* "R0_REG" b0, */ \
{0x00ffffff,0x00000000}, /* "GENERAL_REGS", a0..a7 bo..b7 c0..c7*/ \
{0x00ff0000,0x00000000}, /* "GENERAL_OR_IO_REGS", c0..c7 */ \
{0x03000000,0x00000000}, /* "POINTER_DP1", dp1l dp1h */ \
{0x0c000000,0x00000000}, /* "POINTER_DP2", dp2l dp2h */ \
{0x10000000,0x00000000}, /* "DATA_IDX_SP_REG", i(sp) */ \
{0x60000000,0x00000000}, /* "DATA_REGS", (dp1) (dp2) */ \
{0x80000000,0x00000003}, /* "WINDOWS_REGS", wa wb wc */ \
{0x00000000,0x0000000c}, /* "STACK_POINTER_REGS",spl sph */ \
{0x00000000,0x00000030}, /* "INDX_REGS", idxl idxh */ \
{0x00000000,0x000000c0}, /* "DATA_PAGE_REGS", dp1pg dp2pg */ \
{0x00000000,0x00000100}, /* "HIGH_BYTE_MUL_RES_REG",mrh */ \
{0x00000000,0x00000200}, /* "LOOP_COUNTER_REG", lc */ \
{0x00000000,0x00000c00}, /* "MODES_CONTROL_REGS" dpmode,wcmode */ \
{0x0f000000,0x00000000}, /* "DATA_POINTER_REGS",dp1l,dp1h,dp2l,dp2h */
\
{0x7fffffff,0x00000000}, /* "NO_SYSTEM_REGS" a0..a7 bo..b7 c0..c7 dp1 dp2
(dp1) (dp2) i(sp)*/ \
{0x80000000,0x00000fff}, /* "SYSTEM_REGS",wa wb wc spl sph idxl idxh dp1pg
dp2pg mrh lc dpmode,wcmode*/ \
{0xffffffff,0x00000fff} /* "ALL_REGS" */ \
}
#define BASE_REG_CLASS DATA_POINTER_REGS
#define INDEX_REG_CLASS NO_REGS
There the constraint letters brief description
case 'z' : return R0_REG; /* a0 */
case 'f' : return SYSTEM_REGS; /* wa wb wc spl sph idxl idxh
dp1pg dp2pg mrh lc *//*err*/
case 'a' : return NO_SYSTEM_REGS; /* a0..a7 bo..b7 c0..c7 dp1 dp2
(dp1) (dp2) i(sp)*/
case 'l' : return LOOP_COUNTER_REG; /* lc */
case 'h' : return HIGH_BYTE_MUL_REG; /* mrh */
case 'k' : return DATA_PAGE_REGS; /* dp1pg dp2pg */
case 'x' : return INDX_REGS; /* idxl idxh */
case 'y' : return STACK_POINTER_REGS; /* spl sph */
case 'w' : return WINDOWS_REGS; /* wa wb wc */
case 'd' : return DATA_REGS; /* (dp1) (dp2) */
case 'b' : return DATA_IDX_SP_REG; /* i(sp) */
case 't' : return GENERAL_OR_IO_REGS; /* c0 c1 c2 c3 c4 c5 c6 c7 */
case 'e' : return POINTER_DP1; /* "POINTER_DP1", dp1l dp1h */
case 'j' : return POINTER_DP2; /* "POINTER_DP2", dp2l dp2h */
case 'q' : return DATA_POINTER_REGS; /* dp1,dp2 */
case 'c' : return MODES_CONTROL_REGS; /* "MODES_CONTROL_REGS"
dpmode,wcmode */
I determine EXTRA_CONSTRAINT and EXTRA_MEMORY_CONSTRAINT as follow
#define EXTRA_CONSTRAINT(x, c) extra_constraint(x, c)
where extra_constraint(x, c) is
int
extra_constraint (x, c)
rtx x;
int c;
{
if (c=='R')
return special_symbolref_operand (x, VOIDmode);
if (c == 'S'
&& GET_CODE (x) == MEM
&& GET_CODE (XEXP (x,0)) == REG)
{
rtx xx = XEXP (x,0);
int regno = REGNO (xx);
if (regno >= FIRST_PSEUDO_REGISTER)
{
return TRUE; /* allocate pseudos */
}
else if (regno == REG_DP1)
{
return TRUE; /* strictly check */
}
}
if (c == 'T'
&& GET_CODE (x) == MEM
&& GET_CODE (XEXP (x,0)) == REG)
{
rtx xx = XEXP (x,0);
int regno = REGNO (xx);
if (regno >= FIRST_PSEUDO_REGISTER)
return TRUE; /* allocate pseudos */
}
else if (regno == REG_DP2)
{
return TRUE; /* strictly check */
}
}
return 0;
}
#define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'S'||(C) == 'T')
I define the 16 bit move pattern in MD file like this
(define_expand "movhi"
[(set (match_operand:HI 0 "nonimmediate_operand" "")
(match_operand:HI 1 "general_operand" ""))]
""
"
{
/* One of the ops has to be in a register */
if ( !register_operand(operand0, HImode)
&& !register_operand(operand1, HImode) )
{
operands[1] = copy_to_mode_reg(HImode, operand1);
}
}
")
(define_insn "movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=a, a, a, rtj, rte, S,
T, f, f, j")
(match_operand:HI 1 "general_operand" "a, f, i, S, T , rtj,
rte, a, i, R"))]
"(register_operand (operands[0],HImode)
|| register_operand (operands[1],HImode) )"
"*{
switch (which_alternative)
{
case 0:
return (AS2 (mov,%A0,%A1) CR_TAB
AS2 (mov,%B0,%B1));break;
... and so on.
)
Then I try to compile next simple example
unsigned char S_glob_bytes_1[2]={0x01,0x02};
unsigned char *ptr_1;
unsigned char *ptr_2;
unsigned char *ptr_3;
int main(void)
{
int local_int1;
ptr_1=&S_glob_bytes_1[0];
ptr_2=&S_glob_bytes_1[1];
local_int1=((int)ptr_2)-((int)ptr_1);
ptr_3=ptr_2;
return local_int1;
}
The compiler message
mem_dp2.c: In function `main':
mem_dp2.c:55: error: insn does not satisfy its constraints:
(insn 54 27 29 0x0 (set (reg:HI 24 dp1L [63])
(mem/f:HI (reg/f:HI 24 dp1L [62]) [0 ptr_2+0 S2 A8])) 8 {movhi_internal} (nil)
(nil))
mem_dp2.c:55: internal compiler error: in extract_constrain_insn_cached, at recog.c:2090
Please submit a full bug report,
with preprocessed source if appropriate
.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.
This is LREG dump
;; Function main
Pass 0
Register 49 costs: GENERAL_REGS:0 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:0 ALL_REGS:6000 MEM:8000
Register 50 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 51 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 52 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 53 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 55 costs: GENERAL_REGS:7000 POINTER_DP1:4000 POINTER_DP2:4000
DATA_POINTER_REGS:4000 NO_SYSTEM_REGS:7000 ALL_REGS:10000 MEM:12000
Register 56 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 57 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 58 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 59 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 60 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 61 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 62 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:0 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 63 costs: GENERAL_REGS:6000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:6000 NO_SYSTEM_REGS:6000 ALL_REGS:6000 MEM:8000
Register 66 costs: GENERAL_REGS:7000 POINTER_DP1:4000 POINTER_DP2:4000
DATA_POINTER_REGS:4000 NO_SYSTEM_REGS:7000 ALL_REGS:10000 MEM:12000
Register 67 costs: GENERAL_REGS:3000 POINTER_DP1:0 POINTER_DP2:0
DATA_POINTER_REGS:3000 NO_SYSTEM_REGS:3000 ALL_REGS:6000 MEM:8000
Register 44 pref NO_SYSTEM_REGS or none
Register 45 pref NO_SYSTEM_REGS or none
Register 46 pref NO_SYSTEM_REGS or none
Register 47 pref NO_SYSTEM_REGS or none
Register 48 pref NO_SYSTEM_REGS or none
Register 49 pref NO_SYSTEM_REGS
Register 50 pref DATA_POINTER_REGS
Register 51 pref DATA_POINTER_REGS
Register 52 pref DATA_POINTER_REGS
Register 53 pref DATA_POINTER_REGS
Register 54 pref NO_SYSTEM_REGS or none
Register 55 pref DATA_POINTER_REGS
Register 56 pref DATA_POINTER_REGS
Register 57 pref DATA_POINTER_REGS
Register 58 pref DATA_POINTER_REGS
Register 59 pref DATA_POINTER_REGS
Register 60 pref DATA_POINTER_REGS
Register 61 pref DATA_POINTER_REGS
Register 62 pref DATA_POINTER_REGS
Register 63 pref DATA_POINTER_REGS
Register 64 pref NO_SYSTEM_REGS or none
Register 65 pref NO_SYSTEM_REGS or none
Register 66 pref DATA_POINTER_REGS
Register 67 pref DATA_POINTER_REGS
68 registers.
Register 49 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref NO_SYSTEM_REGS.
Register 50 used 2 times across 3 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 51 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 52 used 2 times across 3 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 53 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 55 used 2 times across 7 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 56 used 2 times across 3 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 57 used 2 times across 3 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 58 used 2 times across 3 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS.
Register 59 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS.
Register 60 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS.
Register 61 used 2 times across 4 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 62 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 63 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS.
Register 66 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 67 used 2 times across 2 insns in block 0; set 1 time; 2 bytes;
pref DATA_POINTER_REGS.
1 basic blocks, 2 edges.
Basic block 0: first insn 47, last 46, prev -1, next -2, loop_depth 0, count
0, freq 0.
Predecessors: ENTRY (fallthru)
Successors: EXIT (fallthru)
Registers live at start: 16 [c0] 17 [c1] 34 [spL]
Registers live at end: 0 [a0] 1 [a1] 16 [c0] 34 [spL]
Invalid sum of outgoing probabilities 0.0%
;; Register 49 in 8.
;; Register 50 in 26.
;; Register 51 in 24.
;; Register 52 in 26.
;; Register 53 in 24.
;; Register 55 in 10.
;; Register 56 in 24.
;; Register 57 in 26.
;; Register 58 in 8.
;; Register 59 in 24.
;; Register 60 in 24.
;; Register 61 in 26.
;; Register 62 in 24.
;; Register 63 in 24.
;; Register 66 in 24.
;; Register 67 in 24.
(note 2 0 3 NOTE_INSN_DELETED)
(note 3 2 47 NOTE_INSN_FUNCTION_BEG)
;; Start of basic block 0, registers live: 16 [c0] 17 [c1] 34 [spL]
(note 47 3 9 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 9 47 10 0 0xa05f2d0 (set (reg/f:HI 50)
(symbol_ref:HI ("ptr_1"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_1"))
(nil)))
(insn 10 9 11 0 0xa05f2d0 (set (reg/f:HI 51)
(symbol_ref:HI ("S_glob_bytes_1"))) 8 {movhi_internal} (nil)
(nil))
(insn 11 10 13 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 50) [0 ptr_1+0 S2 A8])
(reg/f:HI 51)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 51)
(expr_list:REG_DEAD (reg/f:HI 50)
(nil))))
(insn 13 11 14 0 0xa05f2d0 (set (reg/f:HI 52)
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 14 13 15 0 0xa05f2d0 (set (reg/f:HI 53)
(const:HI (plus:HI (symbol_ref:HI ("S_glob_bytes_1"))
(const_int 1 [0x1])))) 8 {movhi_internal} (nil)
(nil))
(insn 15 14 18 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 52) [0 ptr_2+0 S2 A8])
(reg/f:HI 53)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 53)
(expr_list:REG_DEAD (reg/f:HI 52)
(nil))))
(insn 18 15 19 0 0xa05f2d0 (set (reg/f:HI 55)
(plus:HI (reg/f:HI 16 c0)
(const_int -2 [0xfffffffe]))) 15 {addhi3} (nil)
(nil))
(insn 19 18 20 0 0xa05f2d0 (set (reg/f:HI 56)
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 20 19 21 0 0xa05f2d0 (set (reg/f:HI 57)
(symbol_ref:HI ("ptr_1"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_1"))
(nil)))
(insn 21 20 22 0 0xa05f2d0 (set (reg:HI 58)
(mem/f:HI (reg/f:HI 56) [0 ptr_2+0 S2 A8])) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 56)
(nil)))
(insn 22 21 23 0 0xa05f2d0 (set (reg:HI 59)
(mem/f:HI (reg/f:HI 57) [0 ptr_1+0 S2 A8])) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 57)
(nil)))
(insn 23 22 24 0 0xa05f2d0 (set (reg:HI 60)
(minus:HI (reg:HI 58)
(reg:HI 59))) 21 {subhi3} (nil)
(expr_list:REG_DEAD (reg:HI 58)
(expr_list:REG_DEAD (reg:HI 59)
(nil))))
(insn 24 23 26 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 55) [0 local_int1+0 S2
A16])
(reg:HI 60)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg:HI 60)
(expr_list:REG_DEAD (reg/f:HI 55)
(nil))))
(insn 26 24 27 0 0xa05f2d0 (set (reg/f:HI 61)
(symbol_ref:HI ("ptr_3"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_3"))
(nil)))
(insn 27 26 28 0 0xa05f2d0 (set (reg/f:HI 62)
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 28 27 29 0 0xa05f2d0 (set (reg:HI 63)
(mem/f:HI (reg/f:HI 62) [0 ptr_2+0 S2 A8])) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 62)
(nil)))
(insn 29 28 34 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 61) [0 ptr_3+0 S2 A8])
(reg:HI 63)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg:HI 63)
(expr_list:REG_DEAD (reg/f:HI 61)
(nil))))
(insn 34 29 35 0 0xa05f2d0 (set (reg/f:HI 66)
(plus:HI (reg/f:HI 16 c0)
(const_int -2 [0xfffffffe]))) 15 {addhi3} (nil)
(expr_list:REG_DEAD (reg:QI 17 c1)
(nil)))
(insn 35 34 36 0 0xa05f2d0 (set (reg:HI 67)
(mem/f:HI (reg/f:HI 66) [0 local_int1+0 S2 A16])) 8 {movhi_internal}
(nil)
(expr_list:REG_DEAD (reg/f:HI 66)
(nil)))
(insn 36 35 40 0 0xa05f2d0 (set (reg:HI 49)
(reg:HI 67)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg:HI 67)
(nil)))
(note 40 36 43 0 NOTE_INSN_FUNCTION_END)
(insn 43 40 46 0 0xa05f300 (set (reg/i:HI 0 a0)
(reg:HI 49)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg:HI 49)
(nil)))
(insn 46 43 0 0 0xa05f300 (use (reg/i:HI 0 a0)) -1 (nil)
(nil))
;; End of basic block 0, registers live:
0 [a0] 1 [a1] 16 [c0] 34 [spL]
This is GREG dump
;; Function main
Spilling for insn 18.
Spilling for insn 23.
Spilling for insn 24.
Using reg 26 for reload 0
Spilling for insn 28.
Spilling for insn 34.
Spilling for insn 35.
Spilling for insn 18.
Spilling for insn 23.
Spilling for insn 24.
Using reg 26 for reload 0
Spilling for insn 28.
Spilling for insn 34.
Spilling for insn 35.
Reloads for insn # 18
Reload 0: reload_in (HI) = (reg/f:HI 16 c0)
reload_out (HI) = (reg/f:HI 10 b2 [55])
NO_SYSTEM_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/f:HI 16 c0)
reload_out_reg: (reg/f:HI 10 b2 [55])
reload_reg_rtx: (reg/f:HI 10 b2 [55])
Reloads for insn # 23
Reload 0: reload_in (HI) = (reg:HI 8 b0 [58])
reload_out (HI) = (reg:HI 24 dp1L [60])
NO_SYSTEM_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg:HI 8 b0 [58])
reload_out_reg: (reg:HI 24 dp1L [60])
reload_reg_rtx: (reg:HI 8 b0)
Reloads for insn # 24
Reload 0: reload_in (HI) = (reg/f:HI 10 b2 [55])
DATA_POINTER_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0)
reload_in_reg: (reg/f:HI 10 b2 [55])
reload_reg_rtx: (reg:HI 26 dp2L)
Reloads for insn # 28
Reload 0: reload_in (HI) = (mem/f:HI (reg/f:HI 24 dp1L [62]) [0 ptr_2+0 S2
A8])
NO_SYSTEM_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (mem/f:HI (reg/f:HI 24 dp1L [62]) [0 ptr_2+0 S2 A8])
reload_reg_rtx: (reg:HI 24 dp1L [63])
Reloads for insn # 34
Reload 0: reload_in (HI) = (reg/f:HI 16 c0)
reload_out (HI) = (reg/f:HI 24 dp1L [66])
NO_SYSTEM_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/f:HI 16 c0)
reload_out_reg: (reg/f:HI 24 dp1L [66])
reload_reg_rtx: (reg/f:HI 24 dp1L [66])
Reloads for insn # 35
Reload 0: reload_in (HI) = (mem/f:HI (reg/f:HI 24 dp1L [66]) [0 local_int1+0
S2 A16])
NO_SYSTEM_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (mem/f:HI (reg/f:HI 24 dp1L [66]) [0 local_int1+0 S2
A16])
reload_reg_rtx: (reg:HI 24 dp1L [67])
;; Register dispositions:
49 in 8 50 in 26 51 in 24 52 in 26 53 in 24 55 in 10
56 in 24 57 in 26 58 in 8 59 in 24 60 in 24 61 in 26
62 in 24 63 in 24 66 in 24 67 in 24
;; Hard regs used: 0 1 8 9 10 11 16 24 25 26 27
(note 2 0 3 NOTE_INSN_DELETED)
(note 3 2 47 NOTE_INSN_FUNCTION_BEG)
;; Start of basic block 0, registers live: 16 [c0] 17 [c1] 34 [spL]
(note 47 3 9 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 9 47 10 0 0xa05f2d0 (set (reg/f:HI 26 dp2L [50])
(symbol_ref:HI ("ptr_1"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_1"))
(nil)))
(insn 10 9 11 0 0xa05f2d0 (set (reg/f:HI 24 dp1L [51])
(symbol_ref:HI ("S_glob_bytes_1"))) 8 {movhi_internal} (nil)
(nil))
(insn 11 10 13 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 26 dp2L [50]) [0 ptr_1+0
S2 A8])
(reg/f:HI 24 dp1L [51])) 8 {movhi_internal} (nil)
(nil))
(insn 13 11 14 0 0xa05f2d0 (set (reg/f:HI 26 dp2L [52])
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 14 13 15 0 0xa05f2d0 (set (reg/f:HI 24 dp1L [53])
(const:HI (plus:HI (symbol_ref:HI ("S_glob_bytes_1"))
(const_int 1 [0x1])))) 8 {movhi_internal} (nil)
(nil))
(insn 15 14 51 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 26 dp2L [52]) [0 ptr_2+0
S2 A8])
(reg/f:HI 24 dp1L [53])) 8 {movhi_internal} (nil)
(nil))
(insn 51 15 18 0 0x0 (set (reg/f:HI 10 b2 [55])
(reg/f:HI 16 c0)) 8 {movhi_internal} (nil)
(nil))
(insn 18 51 19 0 0xa05f2d0 (set (reg/f:HI 10 b2 [55])
(plus:HI (reg/f:HI 10 b2 [55])
(const_int -2 [0xfffffffe]))) 15 {addhi3} (nil)
(nil))
(insn 19 18 20 0 0xa05f2d0 (set (reg/f:HI 24 dp1L [56])
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 20 19 21 0 0xa05f2d0 (set (reg/f:HI 26 dp2L [57])
(symbol_ref:HI ("ptr_1"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_1"))
(nil)))
(insn 21 20 22 0 0xa05f2d0 (set (reg:HI 8 b0 [58])
(mem/f:HI (reg/f:HI 24 dp1L [56]) [0 ptr_2+0 S2 A8])) 8
{movhi_internal} (nil)
(nil))
(insn 22 21 23 0 0xa05f2d0 (set (reg:HI 24 dp1L [59])
(mem/f:HI (reg/f:HI 26 dp2L [57]) [0 ptr_1+0 S2 A8])) 8
{movhi_internal} (nil)
(nil))
(insn 23 22 52 0 0xa05f2d0 (set (reg:HI 8 b0)
(minus:HI (reg:HI 8 b0)
(reg:HI 24 dp1L [59]))) 21 {subhi3} (nil)
(nil))
(insn 52 23 53 0 0x0 (set (reg:HI 24 dp1L [60])
(reg:HI 8 b0)) 8 {movhi_internal} (nil)
(nil))
(insn 53 52 24 0 0x0 (set (reg:HI 26 dp2L)
(reg/f:HI 10 b2 [55])) 8 {movhi_internal} (nil)
(nil))
(insn 24 53 26 0 0xa05f2d0 (set (mem/f:HI (reg:HI 26 dp2L) [0 local_int1+0
S2 A16])
(reg:HI 24 dp1L [60])) 8 {movhi_internal} (nil)
(nil))
(insn 26 24 27 0 0xa05f2d0 (set (reg/f:HI 26 dp2L [61])
(symbol_ref:HI ("ptr_3"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_3"))
(nil)))
(insn 27 26 54 0 0xa05f2d0 (set (reg/f:HI 24 dp1L [62])
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 54 27 28 0 0x0 (set (reg:HI 24 dp1L [63])
(mem/f:HI (reg/f:HI 24 dp1L [62]) [0 ptr_2+0 S2 A8])) 8
{movhi_internal} (nil)
(nil))
(insn 28 54 29 0 0xa05f2d0 (set (reg:HI 24 dp1L [63])
(reg:HI 24 dp1L [63])) 8 {movhi_internal} (nil)
(nil))
(insn 29 28 55 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 26 dp2L [61]) [0 ptr_3+0
S2 A8])
(reg:HI 24 dp1L [63])) 8 {movhi_internal} (nil)
(nil))
(insn 55 29 34 0 0x0 (set (reg/f:HI 24 dp1L [66])
(reg/f:HI 16 c0)) 8 {movhi_internal} (nil)
(nil))
(insn 34 55 56 0 0xa05f2d0 (set (reg/f:HI 24 dp1L [66])
(plus:HI (reg/f:HI 24 dp1L [66])
(const_int -2 [0xfffffffe]))) 15 {addhi3} (nil)
(nil))
(insn 56 34 35 0 0x0 (set (reg:HI 24 dp1L [67])
(mem/f:HI (reg/f:HI 24 dp1L [66]) [0 local_int1+0 S2 A16])) 8
{movhi_internal} (nil)
(nil))
(insn 35 56 36 0 0xa05f2d0 (set (reg:HI 24 dp1L [67])
(reg:HI 24 dp1L [67])) 8 {movhi_internal} (nil)
(nil))
(insn 36 35 40 0 0xa05f2d0 (set (reg:HI 8 b0 [49])
(reg:HI 24 dp1L [67])) 8 {movhi_internal} (nil)
(nil))
(note 40 36 43 0 NOTE_INSN_FUNCTION_END)
(insn 43 40 46 0 0xa05f300 (set (reg/i:HI 0 a0)
(reg:HI 8 b0 [49])) 8 {movhi_internal} (nil)
(nil))
(insn 46 43 50 0 0xa05f300 (use (reg/i:HI 0 a0)) -1 (nil)
(nil))
;; End of basic block 0, registers live:
0 [a0] 1 [a1] 16 [c0] 34 [spL]
(note 50 46 0 NOTE_INSN_DELETED)
I get wrong code after reload of insn 28.
I have next insn during LREG
(insn 26 24 27 0 0xa05f2d0 (set (reg/f:HI 61)
(symbol_ref:HI ("ptr_3"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_3"))
(nil)))
(insn 27 26 28 0 0xa05f2d0 (set (reg/f:HI 62)
(symbol_ref:HI ("ptr_2"))) 8 {movhi_internal} (nil)
(expr_list:REG_EQUAL (symbol_ref:HI ("ptr_2"))
(nil)))
(insn 28 27 29 0 0xa05f2d0 (set (reg:HI 63)
(mem/f:HI (reg/f:HI 62) [0 ptr_2+0 S2 A8])) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 62)
(nil)))
(insn 29 28 34 0 0xa05f2d0 (set (mem/f:HI (reg/f:HI 61) [0 ptr_3+0 S2 A8])
(reg:HI 63)) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg:HI 63)
(expr_list:REG_DEAD (reg/f:HI 61)
(nil))))
insn 26 prepare pointer (ptr_3) in pseudo 61
insn 27 prapare pointer (ptr_2) in pseudo 62
insn 28 copy from memory mem(reg:62)to intermediate pseudo register 63
insn 28 copy from intermediate pseudo register 63 to memory mem(reg:61)
It seems everything right.
But reloading phase reloads mem(reg:62) in to hard dp1L register and add
wrong instruction
(insn 54 27 28 0 0x0 (set (reg:HI 24 dp1L [63])
(mem/f:HI (reg/f:HI 24 dp1L [62]) [0 ptr_2+0 S2 A8])) 8
{movhi_internal} (nil)
(nil))
(insn 28 54 29 0 0xa05f2d0 (set (reg:HI 24 dp1L [63])
(reg:HI 24 dp1L [63])) 8 {movhi_internal} (nil)
(nil))
I don't understand why reload phase make reload operand mem(reg:62) to hard
register instead of allocation of pseudo 63 in GENERAL_REGS.
More over the compiler should know that impossible to use the address during
insn.
What should I do to escape this situation?
Ildar F. Kaibyshev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Reloading does not proper work on my new 8 bit target, please help
2004-03-16 14:22 Reloading does not proper work on my new 8 bit target, please help ildar
@ 2004-03-16 17:12 ` Joern Rennecke
2004-03-18 9:43 ` ildar
0 siblings, 1 reply; 6+ messages in thread
From: Joern Rennecke @ 2004-03-16 17:12 UTC (permalink / raw)
To: ildar; +Cc: gcc
> #define EXTRA_MEMORY_CONSTRAINT(C) ((C) == 'S'||(C) == 'T')
...
> (define_insn "movhi_internal"
> [(set (match_operand:HI 0 "nonimmediate_operand" "=a, a, a, rtj, rte, S,
> T, f, f, j")
> (match_operand:HI 1 "general_operand" "a, f, i, S, T , rtj,
> rte, a, i, R"))]
> "(register_operand (operands[0],HImode)
> || register_operand (operands[1],HImode) )"
> "*{
> switch (which_alternative)
> {
> case 0:
> return (AS2 (mov,%A0,%A1) CR_TAB
> AS2 (mov,%B0,%B1));break;
> ... and so on.
> )
This is not valid. Look up EXTRA_MEMORY_CONSTRAINT in tm.texi.
You need to combine S and T into one constraint, say U, which can be
EXTRA_MEMORY_CONSTRAINT; S and T by themselves can't.
Then you can use "=a,a,a,rt,j,e,S,T,f,f,j" / "a,f,i,U,S,T,rtj,rte,a,i,R" .
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Reloading does not proper work on my new 8 bit target, please help
2004-03-16 17:12 ` Joern Rennecke
@ 2004-03-18 9:43 ` ildar
2004-03-18 13:13 ` Joern Rennecke
2004-03-18 13:43 ` Joern Rennecke
0 siblings, 2 replies; 6+ messages in thread
From: ildar @ 2004-03-18 9:43 UTC (permalink / raw)
To: joern.rennecke; +Cc: gcc
Thank you for advice a lot.
It seems that I begin to understand the reload entity.
I tried the constraints that you propose, but anyway I have the problem with
generation correct reload code. That is why I decide to simplify the
constraints as it possible.
Now there is MOVHI pattern.
(define_insn "movhi_internal"
[(set (match_operand:HI 0 "nonimmediate_operand" "=a, a, a, rt, m, f, f,
j")
(match_operand:HI 1 "general_operand" "a, f, i, m, rt, a, i,
R"))]
"(register_operand (operands[0],HImode)
|| register_operand (operands[1],HImode) )"
"*{
switch (which_alternative)
{
case 0:
return (AS2 (mov,%A0,%A1) CR_TAB
AS2 (mov,%B0,%B1));break;
case 1:
return (AS2 (mfpr,%A0,%A1) CR_TAB
AS2 (mfpr,%B0,%B1));break;
case 2:
return (AS2 (movl,%A0,low(%1)) CR_TAB
AS2 (movl,%B0,hi(%1)));break;
case 3:
{
rtx d_x=XEXP(operands[1],0);
if (GET_CODE(d_x)==REG
&& true_regnum (d_x)>0)
{
if(REGNO (d_x) == REG_DP1)
{
return (AS2(mov,%A0,(dp1)) CR_TAB
AS2(addl,dp1L,1) CR_TAB
AS1(adc,dp1H) CR_TAB
AS2(mov,%B0,(dp1)) CR_TAB
AS2(subl,dp1L,1) CR_TAB
AS1(sbb,dp1H));
}
if(REGNO (d_x) == REG_DP2)
{
return (AS2(mov,%A0,(dp2)) CR_TAB
AS2(addl,dp2L,1) CR_TAB
AS1(adc,dp2H) CR_TAB
AS2(mov,%B0,(dp2)) CR_TAB
AS2(subl,dp2L,1) CR_TAB
AS1(sbb,dp2H));
}
}
return AS2(REG_DP1,bug,movhi_r_m);
} break;
. . . so on
)
I forbid generating code to load registers of class DATA_POINTER_REGS direct
from memory explicitly.
But after compiling the test compile/20000211-1.c from gcc test suite I get
invalid instruction:
/home/t/compiler2/gcc-unc80-3-3-2/gcc/testsuite/gcc.c-torture/compile/200002
11-1.c: In function `doprnt_1':
/home/t/compiler2/gcc-unc80-3-3-2/gcc/testsuite/gcc.c-torture/compile/200002
11-1.c:81: error: insn does not satisfy its constraints:
(insn 445 144 146 0x0 (set (reg/f:HI 24 dp1L [142])
(mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2 A16])) 8
{movhi_internal} (nil)
(nil))
/home/t/compiler2/gcc-unc80-3-3-2/gcc/testsuite/gcc.c-torture/compile/200002
11-1.c:81: internal compiler error: in extract_constrain_insn_cached, at
recog.c:2090
Please submit a full bug report,
with preprocessed source if appropriate.
See <URL:http://gcc.gnu.org/bugs.html> for instructions.
There are the parts of dump listing in LREG phase.
. . .
Register 142 costs: GENERAL_REGS:2000 POINTER_DP1:2000 POINTER_DP2:2000
DATA_POINTER_REGS:2000 NO_SYSTEM_REGS:4000 ALL_REGS:4000 MEM:8000
Register 144 costs: GENERAL_REGS:6000 POINTER_DP1:4000 POINTER_DP2:4000
DATA_POINTER_REGS:4000 NO_SYSTEM_REGS:6000 ALL_REGS:8000 MEM:12000
. . .
Register 142 pref DATA_POINTER_REGS
Register 143 pref NO_SYSTEM_REGS or none
Register 144 pref DATA_POINTER_REGS
. . .
Register 142 used 2 times across 2 insns in block 7; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
Register 144 used 2 times across 2 insns in block 7; set 1 time; 2 bytes;
pref DATA_POINTER_REGS; pointer.
. . .
;; Register 142 in 24.
;; Register 144 in 24.
. . .
(insn 144 142 145 7 0xa0608d0 (set (reg/f:HI 144)
(plus:HI (reg/f:HI 16 c0)
(const_int -13 [0xfffffff3]))) 15 {addhi3} (nil)
(nil))
(insn 145 144 146 7 0xa0608d0 (set (reg/f:HI 142)
(mem/f:HI (reg/f:HI 144) [0 lstr+0 S2 A16])) 8 {movhi_internal}
(nil)
(expr_list:REG_DEAD (reg/f:HI 144)
(nil)))
(insn 146 145 147 7 0xa0608d0 (set (reg:HI 145)
(mem/s:HI (reg/f:HI 142) [0 S2 A8])) 8 {movhi_internal} (nil)
(expr_list:REG_DEAD (reg/f:HI 142)
(nil)))
. . .
The insn 144 load address in to reg/f:HI 144. This is the address of object
lying on the frame of current function.
The insn 145 get this object from memory and put it to reg/f:HI 142.
We can see that this object is a pointer, that is why reg:142 has preferred
DATA_POINTER_REGS.
The insn 146 get the object and reg:142 points where this object is in
memory.
I see that the price of class preference for reg:142 the same for
GENERAL_REGS and for one of the POINTERS. I suppose that is not correct,
because if class preference of reg/f:HI 142 is GENERAL_REGS then next phase
should generate additional insn to reload value to register of correct
class - one of POINTERs.
If I am right, how I can change the price of class preference for reg:142.
There are the parts of dump listing in GREG phase.
. . .
Reloads for insn # 144
Reload 0: reload_in (HI) = (reg/f:HI 16 c0)
reload_out (HI) = (reg/f:HI 24 dp1L [144])
NO_SYSTEM_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/f:HI 16 c0)
reload_out_reg: (reg/f:HI 24 dp1L [144])
reload_reg_rtx: (reg/f:HI 24 dp1L [144])
Reloads for insn # 145
Reload 0: reload_in (HI) = (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2
A16])
NO_SYSTEM_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2 A16])
reload_reg_rtx: (reg/f:HI 24 dp1L [142])
. . .
(insn 444 142 144 7 0x0 (set (reg/f:HI 24 dp1L [144])
(reg/f:HI 16 c0)) 8 {movhi_internal} (nil)
(nil))
(insn 144 444 445 7 0xa0608d0 (set (reg/f:HI 24 dp1L [144])
(plus:HI (reg/f:HI 24 dp1L [144])
(const_int -13 [0xfffffff3]))) 15 {addhi3} (nil)
(nil))
(insn 445 144 145 7 0x0 (set (reg/f:HI 24 dp1L [142])
(mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2 A16])) 8
{movhi_internal} (nil)
(nil))
(insn 145 445 146 7 0xa0608d0 (set (reg/f:HI 24 dp1L [142])
(reg/f:HI 24 dp1L [142])) 8 {movhi_internal} (nil)
(nil))
(insn 146 145 147 7 0xa0608d0 (set (reg:HI 8 b0 [145])
(mem/s:HI (reg/f:HI 24 dp1L [142]) [0 S2 A8])) 8 {movhi_internal}
(nil)
(nil))
. . .
I see that incorrect instruction insn 445 is generated during reloading for
insn 145. How can I correct this situation?
Ildar F. Kaibyshev
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Reloading does not proper work on my new 8 bit target, please help
2004-03-18 9:43 ` ildar
@ 2004-03-18 13:13 ` Joern Rennecke
2004-03-18 14:31 ` ildar
2004-03-18 13:43 ` Joern Rennecke
1 sibling, 1 reply; 6+ messages in thread
From: Joern Rennecke @ 2004-03-18 13:13 UTC (permalink / raw)
To: ildar; +Cc: joern.rennecke, gcc
> Reloads for insn # 145
>
> Reload 0: reload_in (HI) = (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2
> A16])
>
> NO_SYSTEM_REGS, RELOAD_FOR_INPUT (opnum = 1)
>
> reload_in_reg: (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2 A16])
>
> reload_reg_rtx: (reg/f:HI 24 dp1L [142])
When you want to reload a memory operand into dp1L, you might need
a secondary reload, as in this example. Likewise for dp2L for
memory operands using dp2L. Make sure this is reflected in
SECONDARY_RELOAD_CLASS. (or SECONDARY_INPUT_RELOAD_CLASS &
SECONDARY_OUTPUT_RELOAD_CLASS if you need to make them different).
If you defined MEMORY_MOVE_COST, also make sure that you take
memory_move_secondary_cost into account.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Reloading does not proper work on my new 8 bit target, please help
2004-03-18 9:43 ` ildar
2004-03-18 13:13 ` Joern Rennecke
@ 2004-03-18 13:43 ` Joern Rennecke
1 sibling, 0 replies; 6+ messages in thread
From: Joern Rennecke @ 2004-03-18 13:43 UTC (permalink / raw)
To: ildar; +Cc: joern.rennecke, gcc
P.S.: For performance, you might also want to look at PREFERRED_RELOAD_CLASS.
^ permalink raw reply [flat|nested] 6+ messages in thread
* Re: Reloading does not proper work on my new 8 bit target, please help
2004-03-18 13:13 ` Joern Rennecke
@ 2004-03-18 14:31 ` ildar
0 siblings, 0 replies; 6+ messages in thread
From: ildar @ 2004-03-18 14:31 UTC (permalink / raw)
To: joern.rennecke; +Cc: gcc
> Reloads for insn # 145
>
> Reload 0: reload_in (HI) = (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0
S2
> A16])
>
> NO_SYSTEM_REGS, RELOAD_FOR_INPUT (opnum = 1)
>
> reload_in_reg: (mem/f:HI (reg/f:HI 24 dp1L [144]) [0 lstr+0 S2
A16])
>
> reload_reg_rtx: (reg/f:HI 24 dp1L [142])
>
> When you want to reload a memory operand into dp1L, you might need
> a secondary reload, as in this example. Likewise for dp2L for
> memory operands using dp2L. Make sure this is reflected in
> SECONDARY_RELOAD_CLASS. (or SECONDARY_INPUT_RELOAD_CLASS &
> SECONDARY_OUTPUT_RELOAD_CLASS if you need to make them different).
> If you defined MEMORY_MOVE_COST, also make sure that you take
> memory_move_secondary_cost into account.
The problem is that I don't want such kind reload, that is why I don't
define SECONDARY_RELOAD_CLASS.
It seems that compiler should generate code like this
mem(dp1L) -> dp2L
mem(dp2L) ->(b0),
but compiler generate
mem(dp1L) -> dp1L
dp1L -> dp1L
mem(dp1L) ->b0,
because the class price for register are the same in GENERAL_REGS,
POINTER_DP1, POINTER_DP2 classes, and compiler takes the first suitable
register in class witch can be used as BASE_REG_CLASS without constraint
checking. This class is POINTER_DP1 (see the parts of dump of LREG
phase).
I don't understand why compiler does not check that register in POINTER_DP1
class is already used in the insn.
I suppose if I can decrease the class price for GENERAL_REGS and the price
of GENERAL_REGS becomes less than the class price for POINTER_DP1 or
POINTER_DP2, the compiler should generate correct code like this
mem(dp1L) -> b0 (or another register of GENERAL_REGS )
b0 -> dp2L
mem(dp2L) ->b0.
The question is How can I decrease the class price?
^ permalink raw reply [flat|nested] 6+ messages in thread
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2004-03-16 14:22 Reloading does not proper work on my new 8 bit target, please help ildar
2004-03-16 17:12 ` Joern Rennecke
2004-03-18 9:43 ` ildar
2004-03-18 13:13 ` Joern Rennecke
2004-03-18 14:31 ` ildar
2004-03-18 13:43 ` Joern Rennecke
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