Re: Register Allocation

[Nick Ing-Simmons <nick@ing-simmons.net>]

Tm Gccmail <tm_gccmail@kloo.net> writes:
>On Tue, 21 Sep 2004, Adrian Strätling wrote:
>
>> Hi,
>> 
>> I'm working on a target that does support up to 8 parallel instructions, 
>> but they have to be grouped at compile time. The scheduler could do much 
>> better than it currently does if there were less (output) depencies.
>> 
>> Is it possible to tell the register allocator not to reduce the register 
>> count to the minimum?
>
>I think you're trying to do this the wrong way.

Or at least looking in the wrong place.
My c6x port went out of its way to create new psuedo registers
so that 1st scheduling pass could do this. But I seem to recall 
cse kept eliminiating them.


>
>The first scheduling pass is responsible for reordering the instructions
>so the pseudo lifetimes are overlapping. 
>
>This forces the register allocator to allocate the pseudos to different
>hardware registers.
>
>You need to look at why the first scheduling pass isn't reordering the
>instructions on your target.


>
>Toshi