From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 8161 invoked by alias); 6 Oct 2004 11:37:32 -0000 Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org Received: (qmail 8079 invoked from network); 6 Oct 2004 11:37:30 -0000 Received: from unknown (HELO r-rr.iij4u.or.jp) (210.130.0.76) by sourceware.org with SMTP; 6 Oct 2004 11:37:30 -0000 Received: from localhost (frgw.3in.ne.jp [210.251.121.226]) by r-rr.iij4u.or.jp (8.11.6+IIJ/8.11.6) with ESMTP id i96BbRQ26912 for ; Wed, 6 Oct 2004 20:37:28 +0900 (JST) Date: Wed, 06 Oct 2004 12:23:00 -0000 Message-Id: <20041006.203652.68148224.kkojima@rr.iij4u.or.jp> To: gcc@gcc.gnu.org Subject: PR target/16482: first scheduling pass on SH4 From: Kaz Kojima Mime-Version: 1.0 Content-Type: Text/Plain; charset=us-ascii Content-Transfer-Encoding: 7bit X-SW-Source: 2004-10/txt/msg00180.txt.bz2 Hi, PR target/16482 is a regression for sh-elf from 3.4. The following part of gcc.c-torture/unsorted/SFset.c: int glob1; adrreg0limm1_set (float *p0) { p0[10000000] = (float) glob1; } causes a spill failure for sh-elf on mainline with -m4 -O2. It seems that the first insn scheduling which has been enabled for SH-4 on mainline badly interacts with reloading. The .sched file for the problematic function looks like: ;; ====================================================== ;; -- basic block 1 from 15 to 35 -- before reload ;; ====================================================== ;; 0--> 36 r1=`__fpscr_values' :(issue+load_store),nothing,memory ;; 0--> 25 clobber r0 :nothing ;; 0--> 26 clobber r158 :nothing ;; 0--> 24 r0=r158 :issue ;; 1--> 17 r163=`glob1' :(issue+load_store),nothing,memory ;; 1--> 27 use r0 :nothing ;; 2--> 37 =[r1] :d_lock,nothing,(F1+memory),F1*2 ;; 3--> 18 r165=[r163] :(issue+load_store),nothing,memory ;; 4--> 15 r161=0x2625a00 :(issue+load_store),nothing,memory ;; 5--> 33 r1=`__fpscr_values' :(issue+load_store),nothing,memory ;; 6--> 19 {r164=flt(r165);use ;} :issue,F01,F2 ;; 7--> 34 r166=r1+0x4 :issue,int ;; 8--> 20 {[r4+r161]=r164;use ;clobber scratc:(issue+load_store),nothing,memory ;; 9--> 35 =[r166] :d_lock,nothing,(F1+memory),F1*2 ;; Ready list (final): ;; total time = 9 ;; new head = 16 ;; new tail = 35 Thus the first insn scheduling permutes [r4+r161]=r164 into a lifetime of R0 and the spill process needs R0 for the expression for [r4+r161] because SH-4 uses R0 as the base register for the addressing mode with an index register. Does the first insn scheduling for SH-4 take account of such insn which uses R0 implicitly? Or is it a problem of the reload pass? I've tried to inhibit the permutation like above for the basic blocks which have insns with [rN+rM] and R0 liftimes. It works for me, but what is the right thing to do? Regards, kaz