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* function arguments
@ 2004-10-15 12:51 Shinpei Kato
  2004-10-17 17:16 ` pseudo register in reload progress Shinpei Kato
  0 siblings, 1 reply; 2+ messages in thread
From: Shinpei Kato @ 2004-10-15 12:51 UTC (permalink / raw)
  To: gcc

Hi there.

I face a problem about dealing with float-type function arguments.
Assume that an arch has general registers with 32-bit and floating-point
registers with 64-bit.
For example based on MIPS, assuming we write the following code.

float f = 1.23;
printf("%f\n", f);

If we compile this code, a generated assembly code is like:

cvt.d.s $f0,$f0
lui     $2,%hi($LC5)
addiu   $4,$2,%lo($LC5)
mfc1    $6,$f1
mfc1    $5,$f0
jal     printf

this mips assembly looks fp regs as 32-bit, so loading data to argument
regs from fp regs with mfc1. I want to modify them as follows because we
have 32-bit gpr and 64-bit fpr.

cvt.d.s $f0,$f0
lui     $2,%hi($LC5)
addiu   $4,$2,%lo($LC5)
mfc1h   $6,$f0           # upper 32-bit
mfc1    $5,$f0           # lower 32-bit
jal     printf

Is this an issue of move insns? I thought so at first though, now I
think it's an issue of function args.
Which parts of a Machine Discription or Macros/Functions should I modify?

I need your help.

-- 
Shinpei Kato <shinny@j02.itscom.net>

^ permalink raw reply	[flat|nested] 2+ messages in thread

* pseudo register in reload progress
  2004-10-15 12:51 function arguments Shinpei Kato
@ 2004-10-17 17:16 ` Shinpei Kato
  0 siblings, 0 replies; 2+ messages in thread
From: Shinpei Kato @ 2004-10-17 17:16 UTC (permalink / raw)
  To: Shinpei Kato; +Cc: gcc

Hi,

Sorry, I could the previous problem by imploving movdf insns.
However I got a new problem about gen_reg_rtx() function.
To achieve a move pattern of GR reg => FP reg, we need to emit the
following codes.

# store $6 to upper 32-bit of $f0, lower 32-bit is filled with 0
mtc1h   $6,$f0
# store $5 to lower 32-bit of $f1, upper 32-bit is filled with 0
mtc1    $5,$f1
# OR between fp regs
for     $f0, $f0, $f1

Here, $f1 is temporary register. So I wanna use gen_reg_rtx(DFmode) to
create a pseudo register but gen_reg_rtx cannot be used if
no_new_pseudos holds true. I tried to use SECONDARY_INPUT_RELOAD_CLASS
and SECONDARY_OUT_RELOAD_CLASS but SECONDARY_INPUT_RELOAD_CLASS doesn't
allow creating the same secondary register as class. In my case, class
is FP register and secondary register is also FP register I think. So it
fails to compile.
How could I emit codes above to achieve GR reg to FP reg move?
I need your help.

Regards,
Shinpei Kato

^ permalink raw reply	[flat|nested] 2+ messages in thread

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