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Date: Sun, 17 Oct 2004 17:16:00 -0000
From: Shinpei Kato <shinny@j02.itscom.net>
To: Shinpei Kato <shinny@j02.itscom.net>
Subject: pseudo register in reload progress
Cc: gcc@gcc.gnu.org
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Hi,

Sorry, I could the previous problem by imploving movdf insns.
However I got a new problem about gen_reg_rtx() function.
To achieve a move pattern of GR reg => FP reg, we need to emit the
following codes.

# store $6 to upper 32-bit of $f0, lower 32-bit is filled with 0
mtc1h   $6,$f0
# store $5 to lower 32-bit of $f1, upper 32-bit is filled with 0
mtc1    $5,$f1
# OR between fp regs
for     $f0, $f0, $f1

Here, $f1 is temporary register. So I wanna use gen_reg_rtx(DFmode) to
create a pseudo register but gen_reg_rtx cannot be used if
no_new_pseudos holds true. I tried to use SECONDARY_INPUT_RELOAD_CLASS
and SECONDARY_OUT_RELOAD_CLASS but SECONDARY_INPUT_RELOAD_CLASS doesn't
allow creating the same secondary register as class. In my case, class
is FP register and secondary register is also FP register I think. So it
fails to compile.
How could I emit codes above to achieve GR reg to FP reg move?
I need your help.

Regards,
Shinpei Kato