* GCC 3.3.1 -O2 problem with sqrt.c
@ 2005-05-27 13:42 Sanjiv Kumar Gupta
2005-05-27 17:49 ` Ian Lance Taylor
0 siblings, 1 reply; 8+ messages in thread
From: Sanjiv Kumar Gupta @ 2005-05-27 13:42 UTC (permalink / raw)
To: gcc
I am using gcc 3.3.1 release as my port, and looks
like I have hit a problem with greg.
The source program is the sqrt.c math function
__ieee754_sqrt. ( I am pasting the relevent part
here)
typedef union
{
double value;
struct
{
unsigned int lsw;
unsigned int msw;
} parts;
} ieee_double_shape_type;
double
__ieee754_sqrt (double x)
{
double z;
int sign = (int) 0x80000000;
unsigned int r, t1, s1, ix1, q1;
int ix0, s0, q, m, t, i;
..
..
if ((q & 1) == 1)
ix1 |= sign;
ix0 += (m << 20);
do
{
ieee_double_shape_type iw_u;
iw_u.parts.msw = (ix0); // line 140
iw_u.parts.lsw = (ix1); // line 141
(z) = iw_u.value; // line 142
}
}
The dump of corresponding BBs of .23.lreg is as
(insn 419 516 420 38 0x1002f450 (set (reg/v:SI 77)
(ior:SI (reg/v:SI 77)
(const_int -2147483648 [0x80000000]))) 26
{iorsi3} (nil)
(nil))
;; End of basic block 38, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 39, registers live: 20 [r20]
21 [r21] 30 [r30] 64 [ap] 7
7 79 82 153
(code_label 420 419 517 39 43 "" [1 uses])
(note 517 420 421 39 [bb 39] NOTE_INSN_BASIC_BLOCK)
(note 421 517 422 39 ("sqrt.c") 136)
(insn 422 421 423 39 0x1002f450 (set (reg/v:SI 82)
(ashift:SI (reg/v:SI 82)
(const_int 20 [0x14]))) 22 {ashlsi3} (nil)
(nil))
(note 423 422 427 39 NOTE_INSN_DELETED)
(note 427 423 428 39 ("sqrt.c") 139)
(note 428 427 429 39 ("sqrt.c") 140)
(insn 429 428 430 39 0x1002f420 (set (subreg:SI
(reg/v:DI 153) 4)
(plus:SI (reg/v:SI 79)
(reg/v:SI 82))) 12 {addsi3} (insn_list 422
(nil))
(expr_list:REG_DEAD (reg/v:SI 82)
(expr_list:REG_DEAD (reg/v:SI 79)
(nil))))
(note 430 429 431 39 ("sqrt.c") 141)
(insn 431 430 432 39 0x1002f420 (set (subreg:SI
(reg/v:DI 153) 0)
(reg/v:SI 77)) 6 {*movsi} (insn_list 429
(nil))
(expr_list:REG_DEAD (reg/v:SI 77)
(nil)))
(note 432 431 433 39 ("sqrt.c") 142)
(insn 433 432 436 39 0x1002f420 (set (reg:DF 70)
(subreg:DF (reg/v:DI 153) 0)) 10 {*movdf}
(insn_list 431 (nil))
(expr_list:REG_DEAD (reg/v:DI 153)
(nil)))
And the dump of .24.greg pass is as:
(insn 419 516 420 38 0x1002f450 (set (reg/v:SI 12 r12
[77])
(ior:SI (reg/v:SI 12 r12 [77])
(const_int -2147483648 [0x80000000]))) 26
{iorsi3} (nil)
(nil))
;; End of basic block 38, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 39, registers live: 20 [r20]
21 [r21] 30 [r30] 77 79 82
153
(code_label 420 419 517 39 43 "" [1 uses])
(note 517 420 421 39 [bb 39] NOTE_INSN_BASIC_BLOCK)
(note 421 517 422 39 ("sqrt.c") 136)
(insn 422 421 423 39 0x1002f450 (set (reg/v:SI 4 r4
[82])
(ashift:SI (reg/v:SI 4 r4 [82])
(const_int 20 [0x14]))) 22 {ashlsi3} (nil)
(nil))
(note 423 422 427 39 NOTE_INSN_DELETED)
(note 427 423 428 39 ("sqrt.c") 139)
(note 428 427 429 39 ("sqrt.c") 140)
(insn 429 428 618 39 0x1002f420 (set (reg/v:SI 4 r4
[82])
(plus:SI (reg/v:SI 4 r4 [82])
(reg/v:SI 3 r3 [79]))) 12 {addsi3}
(insn_list 422 (nil))
(nil))
(insn 618 429 619 39 0x0 (set (reg:SI 0 r0)
(reg/v:SI 4 r4 [82])) 6 {*movsi} (nil)
(nil))
(insn 619 618 430 39 0x0 (set (mem:SI (plus:SI
(reg/f:SI 21 r21)
(const_int -4 [0xfffffffc])) [3 iw_u
S4 A32])
(reg:SI 0 r0)) 6 {*movsi} (nil)
(nil))
(note 430 619 431 39 ("sqrt.c") 141)
(insn 431 430 620 39 0x1002f420 (set (reg:SI 0 r0)
(reg/v:SI 12 r12 [77])) 6 {*movsi} (insn_list
429 (nil))
(nil))
(insn 620 431 621 39 0x0 (set (reg:DI 2 r2)
(reg:DI 0 r0)) 7 {*movdi} (nil)
(nil))
(insn 621 620 432 39 0x0 (set (mem:DI (plus:SI
(reg/f:SI 21 r21)
(const_int -8 [0xfffffff8])) [3 iw_u
S8 A32])
(reg:DI 2 r2)) 7 {*movdi} (nil)
(nil))
(note 432 621 433 39 ("sqrt.c") 142)
(insn 433 432 436 39 0x1002f420 (set (reg:DF 14 r14
[70])
(reg:DF 0 r0)) 10 {*movdf} (insn_list 431
(nil))
(nil))
I couldn't understand why the insns 620 and 621 are
being generated here as DI moves.
This is creating problem since insn 621 gets splitted
after reload into two SI moves,i.e. @(r21, -8) and
@(r21, -4).
This renders insns 619 as dead and hence insns 618 and
insn 429 as dead, which are eliminated by flow2.
I could not analyze beyond this and need your help to
move further.
Thanks in advance.
Sanjiv
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^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-27 13:42 GCC 3.3.1 -O2 problem with sqrt.c Sanjiv Kumar Gupta
@ 2005-05-27 17:49 ` Ian Lance Taylor
2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-05-30 15:28 ` Sanjiv Kumar Gupta
0 siblings, 2 replies; 8+ messages in thread
From: Ian Lance Taylor @ 2005-05-27 17:49 UTC (permalink / raw)
To: Sanjiv Kumar Gupta; +Cc: gcc
Sanjiv Kumar Gupta <skgnu@yahoo.com> writes:
> I am using gcc 3.3.1 release as my port, and looks
> like I have hit a problem with greg.
You neglected to mention what target you are using.
> I couldn't understand why the insns 620 and 621 are
> being generated here as DI moves.
I'm not sure specifically why it got a DI move here, but it doesn't
look wrong. It's treating the struct named parts as DImode.
> This is creating problem since insn 621 gets splitted
> after reload into two SI moves,i.e. @(r21, -8) and
> @(r21, -4).
> This renders insns 619 as dead and hence insns 618 and
> insn 429 as dead, which are eliminated by flow2.
It does look rather suspicious, but it's hard to know whether it is
wrong without seeing the value in r1.
Does the behaviour change if you use -fno-strict-aliasing? (I can't
remember what the default was in 3.3.1).
Ian
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-27 17:49 ` Ian Lance Taylor
2005-05-30 15:28 ` Sanjiv Kumar Gupta
@ 2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-06-02 13:19 ` Dave Korn
2005-06-04 2:58 ` Ian Lance Taylor
1 sibling, 2 replies; 8+ messages in thread
From: Sanjiv Kumar Gupta @ 2005-05-30 15:28 UTC (permalink / raw)
To: Ian Lance Taylor; +Cc: Sanjiv Kumar Gupta, gcc
Ian Lance Taylor wrote:
> Sanjiv Kumar Gupta <skgnu@yahoo.com> writes:
>
>
>>I am using gcc 3.3.1 release as my port, and looks
>>like I have hit a problem with greg.
>
>
> You neglected to mention what target you are using.
>
Ian, the port is for a 32-bit RISC and not complete yet,
hence still not contributed.
This probably makes difficult for you to suggest any
fix, but I still asked in case I could get any pointers
for investigation.
>
>>I couldn't understand why the insns 620 and 621 are
>>being generated here as DI moves.
>
>
> I'm not sure specifically why it got a DI move here, but it doesn't
> look wrong. It's treating the struct named parts as DImode.
>
>
>>This is creating problem since insn 621 gets splitted
>>after reload into two SI moves,i.e. @(r21, -8) and
>>@(r21, -4).
>>This renders insns 619 as dead and hence insns 618 and
>>insn 429 as dead, which are eliminated by flow2.
>
>
> It does look rather suspicious, but it's hard to know whether it is
> wrong without seeing the value in r1.
>
r1 looks unrelated to struct members, and is being used by the
ifcvt pass to expand some comparison insns.
> Does the behaviour change if you use -fno-strict-aliasing? (I can't
> remember what the default was in 3.3.1).
>
> Ian
>
The behaviour doesn't changes with -fno-strict-aliasing or
-fstrict-aliasing.
Thanks
Sanjiv
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-27 17:49 ` Ian Lance Taylor
@ 2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-05-31 12:13 ` Sanjiv Kumar Gupta
2005-05-30 15:28 ` Sanjiv Kumar Gupta
1 sibling, 1 reply; 8+ messages in thread
From: Sanjiv Kumar Gupta @ 2005-05-30 15:28 UTC (permalink / raw)
To: Ian Lance Taylor; +Cc: gcc
[-- Attachment #1: Type: text/plain, Size: 1309 bytes --]
Ian,
I am attaching full .greg file here, in case
it helps. I don't know whether gcc mail server
accepts attachments or not, hence didn't send
it to the list.
Thanks
Sanjiv
--- Ian Lance Taylor <ian@airs.com> wrote:
> Sanjiv Kumar Gupta <skgnu@yahoo.com> writes:
>
> > I am using gcc 3.3.1 release as my port, and looks
> > like I have hit a problem with greg.
>
> You neglected to mention what target you are using.
>
> > I couldn't understand why the insns 620 and 621
> are
> > being generated here as DI moves.
>
> I'm not sure specifically why it got a DI move here,
> but it doesn't
> look wrong. It's treating the struct named parts as
> DImode.
>
> > This is creating problem since insn 621 gets
> splitted
> > after reload into two SI moves,i.e. @(r21, -8) and
> > @(r21, -4).
> > This renders insns 619 as dead and hence insns 618
> and
> > insn 429 as dead, which are eliminated by flow2.
>
> It does look rather suspicious, but it's hard to
> know whether it is
> wrong without seeing the value in r1.
>
> Does the behaviour change if you use
> -fno-strict-aliasing? (I can't
> remember what the default was in 3.3.1).
>
> Ian
>
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[-- Attachment #2: 582424730-sqrt.c.24.greg --]
[-- Type: application/octet-stream, Size: 71214 bytes --]
;; Function __ieee754_sqrt
;; 17 regs to allocate: 83 79 168 77 74 75 70 (2) 71 (2) 131 84 80 82 76 81 78 72 (2) 153 (2)
;; 70 conflicts: 70 71 77 79 97 153 0 17 18 20 30
;; 71 conflicts: 70 71 77 79 85 86 91 97 101 104 153 0 1 4 5 6 16 17 18 19 20 30
;; 72 conflicts: 72 78 81 82 143 153 0 16 17 18 19 20 30
;; 73 conflicts: 73 74 76 77 78 79 80 81 82 153 0 20 30
;; 74 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30
;; 75 conflicts: 74 75 76 77 78 79 80 81 82 83 131 133 134 153 164 168 170 0 1 20 30
;; 76 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30
;; 77 conflicts: 70 71 73 74 75 76 77 78 79 80 81 82 83 84 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 153 155 164 168 170 0 1 17 18 20 30
;; 78 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 143 148 149 153 164 168 170 176 177 0 1 16 17 18 19 20 30
;; 79 conflicts: 70 71 73 74 75 76 77 78 79 80 81 82 83 84 85 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 153 155 164 168 170 0 1 17 18 20 30
;; 80 conflicts: 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 153 164 168 170 0 1 20 30
;; 81 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 128 129 131 133 134 136 137 143 148 149 153 164 168 170 176 177 0 1 16 17 18 19 20 30
;; 82 conflicts: 72 73 74 75 76 77 78 79 80 81 82 83 84 113 114 116 118 120 122 123 125 126 128 129 131 133 134 136 137 143 148 149 153 155 164 168 170 176 177 0 1 16 17 18 19 20 30
;; 83 conflicts: 74 75 76 77 78 79 80 81 82 83 131 133 134 153 164 168 170 0 1 20 30
;; 84 conflicts: 77 79 82 84 114 115 116 118 153 155 0 20 30
;; 85 conflicts: 71 79 85 153 0 1 17 18 20 30
;; 86 conflicts: 71 77 79 86 153 0 17 18 20 30
;; 91 conflicts: 71 91 18 19 20 30
;; 97 conflicts: 70 71 77 79 97 153 0 17 18 20 30
;; 101 conflicts: 71 101 104 0 4 5 6 16 17 18 19 20 30
;; 104 conflicts: 71 101 104 108 0 1 4 5 6 16 17 18 19 20 30
;; 108 conflicts: 104 108 0 1 4 5 17 18 19 20 30
;; 113 conflicts: 77 79 82 113 153 0 20 30
;; 114 conflicts: 77 79 82 84 114 153 0 20 30
;; 115 conflicts: 77 79 84 115 153 0 20 30
;; 116 conflicts: 77 79 82 84 116 153 0 20 30
;; 118 conflicts: 77 79 82 84 118 153 0 20 30
;; 120 conflicts: 77 79 82 120 153 0 20 30
;; 122 conflicts: 77 79 82 122 153 0 20 30
;; 123 conflicts: 77 79 82 123 153 0 20 30
;; 125 conflicts: 77 79 82 125 153 0 20 30
;; 126 conflicts: 77 79 82 126 153 0 20 30
;; 128 conflicts: 74 76 77 78 79 80 81 82 128 153 0 20 30
;; 129 conflicts: 74 76 77 78 79 80 81 82 129 153 0 20 30
;; 131 conflicts: 74 75 76 77 78 79 80 81 82 83 131 153 168 20 30
;; 133 conflicts: 74 75 76 77 78 79 80 81 82 83 133 153 0 20 30
;; 134 conflicts: 74 75 76 77 78 79 80 81 82 83 134 153 170 0 1 20 30
;; 136 conflicts: 74 76 77 78 79 80 81 82 136 153 0 20 30
;; 137 conflicts: 74 76 77 78 79 80 81 82 137 153 0 20 30
;; 143 conflicts: 72 78 81 82 143 153 18 20 30
;; 148 conflicts: 78 81 82 148 153 18 20 30
;; 149 conflicts: 78 81 82 149 153 0 20 30
;; 153 conflicts: 70 71 72 73 74 75 76 77 78 79 80 81 82 83 84 85 86 97 113 114 115 116 118 120 122 123 125 126 128 129 131 133 134 136 137 143 148 149 153 155 164 168 170 176 177 0 1 16 17 18 19 20 30
;; 155 conflicts: 77 79 82 84 153 155 0 20 30
;; 164 conflicts: 74 75 76 77 78 79 80 81 82 83 153 164 168 0 20 30
;; 168 conflicts: 74 75 76 77 78 79 80 81 82 83 131 153 164 168 0 20 30
;; 170 conflicts: 74 75 76 77 78 79 80 81 82 83 134 153 170 0 1 20 30
;; 176 conflicts: 78 81 82 153 176 177 0 1 20 30
;; 177 conflicts: 78 81 82 153 176 177 0 1 20 30
Spilling for insn 581.
Using reg 0 for reload 0
Using reg 2 for reload 1
Spilling for insn 26.
Spilling for insn 61.
Spilling for insn 111.
Spilling for insn 131.
Spilling for insn 528.
Spilling for insn 147.
Spilling for insn 168.
Spilling for insn 172.
Spilling for insn 173.
Using reg 2 for reload 0
Spilling for insn 184.
Spilling for insn 191.
Spilling for insn 201.
Spilling for insn 225.
Spilling for insn 232.
Spilling for insn 240.
Spilling for insn 269.
Spilling for insn 562.
Spilling for insn 563.
Spilling for insn 294.
Spilling for insn 296.
Spilling for insn 299.
Spilling for insn 568.
Spilling for insn 320.
Spilling for insn 574.
Spilling for insn 575.
Spilling for insn 403.
Spilling for insn 410.
Spilling for insn 413.
Spilling for insn 429.
Using reg 0 for reload 0
Spilling for insn 431.
Using reg 0 for reload 0
Using reg 2 for reload 1
Spilling for insn 433.
Using reg 0 for reload 0
Using reg 0 for reload 1
Reloads for insn # 581
Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p
reload_reg_rtx: (reg:DI 0 r0)
Reload 1: reload_out (DI) = (reg/v:DI 153)
GPR_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:DI 153)
reload_reg_rtx: (reg:DI 2 r2)
secondary_out_reload = 0
Reloads for insn # 26
Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79])
reload_out (SI) = (reg:SI 0 r0 [86])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 3 r3 [79])
reload_out_reg: (reg:SI 0 r0 [86])
reload_reg_rtx: (reg:SI 0 r0 [86])
Reloads for insn # 61
Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79])
reload_out (SI) = (reg:SI 0 r0 [97])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 3 r3 [79])
reload_out_reg: (reg:SI 0 r0 [97])
reload_reg_rtx: (reg:SI 0 r0 [97])
Reloads for insn # 111
Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79])
reload_out (SI) = (reg/v:SI 4 r4 [82])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 3 r3 [79])
reload_out_reg: (reg/v:SI 4 r4 [82])
reload_reg_rtx: (reg/v:SI 4 r4 [82])
Reloads for insn # 131
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [113])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [113])
reload_reg_rtx: (reg:SI 0 r0 [113])
Reloads for insn # 528
Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79])
reload_out (SI) = (reg:SI 0 r0 [155])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 3 r3 [79])
reload_out_reg: (reg:SI 0 r0 [155])
reload_reg_rtx: (reg:SI 0 r0 [155])
Reloads for insn # 147
Reload 0: reload_in (SI) = (reg/v:SI 3 r3 [79])
reload_out (SI) = (reg/s:SI 0 r0 [114])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 3 r3 [79])
reload_out_reg: (reg/s:SI 0 r0 [114])
reload_reg_rtx: (reg/s:SI 0 r0 [114])
Reloads for insn # 168
Reload 0: reload_in (SI) = (reg/v:SI 4 r4 [82])
reload_out (SI) = (reg:SI 0 r0 [115])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 4 r4 [82])
reload_out_reg: (reg:SI 0 r0 [115])
reload_reg_rtx: (reg:SI 0 r0 [115])
Reloads for insn # 172
Reload 0: reload_in (SI) = (reg/v:SI 1 r1 [84])
reload_out (SI) = (reg:SI 0 r0 [116])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 1 r1 [84])
reload_out_reg: (reg:SI 0 r0 [116])
reload_reg_rtx: (reg:SI 0 r0 [116])
Reloads for insn # 173
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [118])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [118])
reload_reg_rtx: (reg:SI 2 r2)
Reloads for insn # 184
Reload 0: reload_in (SI) = (reg/v:SI 4 r4 [82])
reload_out (SI) = (reg:SI 0 r0 [120])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 4 r4 [82])
reload_out_reg: (reg:SI 0 r0 [120])
reload_reg_rtx: (reg:SI 0 r0 [120])
Reloads for insn # 191
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [122])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [122])
reload_reg_rtx: (reg:SI 0 r0 [122])
Reloads for insn # 201
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [125])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [125])
reload_reg_rtx: (reg:SI 0 r0 [125])
Reloads for insn # 225
Reload 0: reload_in (SI) = (reg/v:SI 15 r15 [80])
reload_out (SI) = (reg/v:SI 2 r2 [83])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 15 r15 [80])
reload_out_reg: (reg/v:SI 2 r2 [83])
reload_reg_rtx: (reg/v:SI 2 r2 [83])
Reloads for insn # 232
Reload 0: reload_in (SI) = (reg/v:SI 2 r2 [83])
reload_out (SI) = (reg/v:SI 15 r15 [80])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 2 r2 [83])
reload_out_reg: (reg/v:SI 15 r15 [80])
reload_reg_rtx: (reg/v:SI 15 r15 [80])
Reloads for insn # 240
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [128])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [128])
reload_reg_rtx: (reg:SI 0 r0 [128])
Reloads for insn # 269
Reload 0: reload_in (SI) = (reg/v:SI 17 r17 [76])
reload_out (SI) = (reg/v:SI 14 r14 [75])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 17 r17 [76])
reload_out_reg: (reg/v:SI 14 r14 [75])
reload_reg_rtx: (reg/v:SI 14 r14 [75])
Reloads for insn # 562
Reload 0: reload_in (SI) = (reg/v:SI 2 r2 [83])
reload_out (SI) = (reg:SI 0 r0 [164])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 2 r2 [83])
reload_out_reg: (reg:SI 0 r0 [164])
reload_reg_rtx: (reg:SI 0 r0 [164])
Reloads for insn # 563
Reload 0: reload_in (SI) = (reg:SI 0 r0 [164])
reload_out (SI) = (reg:SI 1 r1 [168])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg:SI 0 r0 [164])
reload_out_reg: (reg:SI 1 r1 [168])
reload_reg_rtx: (reg:SI 1 r1 [168])
Reloads for insn # 294
Reload 0: reload_in (SI) = (reg/v:SI 14 r14 [75])
reload_out (SI) = (reg/v:SI 17 r17 [76])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 14 r14 [75])
reload_out_reg: (reg/v:SI 17 r17 [76])
reload_reg_rtx: (reg/v:SI 17 r17 [76])
Reloads for insn # 296
Reload 0: reload_in (SI) = (reg/v:SI 14 r14 [75])
reload_out (SI) = (reg:SI 0 r0 [133])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 14 r14 [75])
reload_out_reg: (reg:SI 0 r0 [133])
reload_reg_rtx: (reg:SI 0 r0 [133])
Reloads for insn # 299
Reload 0: reload_in (SI) = (reg/v:SI 17 r17 [76])
reload_out (SI) = (reg:SI 1 r1 [134])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 17 r17 [76])
reload_out_reg: (reg:SI 1 r1 [134])
reload_reg_rtx: (reg:SI 1 r1 [134])
Reloads for insn # 568
Reload 0: reload_in (SI) = (reg:SI 1 r1 [134])
reload_out (SI) = (reg:SI 0 r0 [170])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg:SI 1 r1 [134])
reload_out_reg: (reg:SI 0 r0 [170])
reload_reg_rtx: (reg:SI 0 r0 [170])
Reloads for insn # 320
Reload 0: reload_in (SI) = (reg/v:SI 12 r12 [77])
reload_out (SI) = (reg:SI 0 r0 [136])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 12 r12 [77])
reload_out_reg: (reg:SI 0 r0 [136])
reload_reg_rtx: (reg:SI 0 r0 [136])
Reloads for insn # 574
Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78])
reload_out (SI) = (reg:SI 1 r1 [176])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 8 r8 [78])
reload_out_reg: (reg:SI 1 r1 [176])
reload_reg_rtx: (reg:SI 1 r1 [176])
Reloads for insn # 575
Reload 0: reload_in (SI) = (reg:SI 1 r1 [176])
reload_out (SI) = (reg:SI 0 r0 [177])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg:SI 1 r1 [176])
reload_out_reg: (reg:SI 0 r0 [177])
reload_reg_rtx: (reg:SI 0 r0 [177])
Reloads for insn # 403
Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78])
reload_out (SI) = (reg:SI 0 r0 [149])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 8 r8 [78])
reload_out_reg: (reg:SI 0 r0 [149])
reload_reg_rtx: (reg:SI 0 r0 [149])
Reloads for insn # 410
Reload 0: reload_in (SI) = (reg/v:SI 6 r6 [81])
reload_out (SI) = (reg/v:SI 3 r3 [79])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 6 r6 [81])
reload_out_reg: (reg/v:SI 3 r3 [79])
reload_reg_rtx: (reg/v:SI 3 r3 [79])
Reloads for insn # 413
Reload 0: reload_in (SI) = (reg/v:SI 8 r8 [78])
reload_out (SI) = (reg/v:SI 12 r12 [77])
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 8 r8 [78])
reload_out_reg: (reg/v:SI 12 r12 [77])
reload_reg_rtx: (reg/v:SI 12 r12 [77])
Reloads for insn # 429
Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p
reload_reg_rtx: (reg:SI 0 r0)
Reload 1: reload_in (SI) = (reg/v:SI 4 r4 [82])
reload_out (SI) = (subreg:SI (reg/v:DI 153) 4)
GPR_REGS, RELOAD_OTHER (opnum = 0)
reload_in_reg: (reg/v:SI 4 r4 [82])
reload_out_reg: (subreg:SI (reg/v:DI 153) 4)
reload_reg_rtx: (reg/v:SI 4 r4 [82])
secondary_out_reload = 0
Reloads for insn # 431
Reload 0: ADDR32_REGS, RELOAD_FOR_OUTPUT_ADDRESS (opnum = 0), can't combine, secondary_reload_p
reload_reg_rtx: (reg:DI 2 r2)
Reload 1: reload_out (DI) = (reg/v:DI 153)
GPR_REGS, RELOAD_FOR_OUTPUT (opnum = 0)
reload_out_reg: (reg/v:DI 153)
reload_reg_rtx: (reg:DI 0 r0)
secondary_out_reload = 0
Reloads for insn # 433
Reload 0: ADDR32_REGS, RELOAD_FOR_INPUT_ADDRESS (opnum = 1), can't combine, secondary_reload_p
reload_reg_rtx: (reg:DI 2 r2)
Reload 1: reload_in (DI) = (reg/v:DI 153)
GPR_REGS, RELOAD_FOR_INPUT (opnum = 1)
reload_in_reg: (reg/v:DI 153)
reload_reg_rtx: (reg:DI 0 r0)
secondary_in_reload = 0
;; Register dispositions:
70 in 14 71 in 8 72 in 10 73 in 0 74 in 13 75 in 14
76 in 17 77 in 12 78 in 8 79 in 3 80 in 15 81 in 6
82 in 4 83 in 2 84 in 1 85 in 0 86 in 0 91 in 18
97 in 0 101 in 6 104 in 4 108 in 0 113 in 0 114 in 0
115 in 0 116 in 0 118 in 0 120 in 0 122 in 0 123 in 0
125 in 0 126 in 0 128 in 0 129 in 0 131 in 0 133 in 0
134 in 1 136 in 0 137 in 0 143 in 18 148 in 18 149 in 0
155 in 0 164 in 0 168 in 1 170 in 0 176 in 1 177 in 0
;; Hard regs used: 0 1 2 3 4 5 6 8 9 10 11 12 13 14 15 16 17 18 19 21 64
(note 1 0 450 ("sqrt.c") 15)
;; Start of basic block 0, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30]
(note 450 1 581 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 581 450 587 0 0x0 (set (reg:DI 2 r2)
(const_int 0 [0x0])) 7 {*movdi} (nil)
(nil))
(insn 587 581 588 0 0x0 (set (reg:DI 0 r0)
(reg:DI 2 r2)) 7 {*movdi} (nil)
(nil))
(insn 588 587 3 0 0x0 (set (mem:DI (plus:SI (reg/f:SI 21 r21)
(const_int -8 [0xfffffff8])) [3 iw_u S8 A32])
(reg:DI 0 r0)) 7 {*movdi} (nil)
(nil))
(insn 3 588 4 0 0x0 (set (reg/v:DF 8 r8 [71])
(reg:DF 17 r17)) 10 {*movdf} (nil)
(nil))
(note 4 3 8 0 NOTE_INSN_FUNCTION_BEG)
(note 8 4 9 0 ("sqrt.c") 16)
(note 9 8 11 0 ("sqrt.c") 17)
(note 11 9 12 0 ("sqrt.c") 18)
(note 12 11 16 0 ("sqrt.c") 19)
(note 16 12 17 0 ("sqrt.c") 23)
(note 17 16 18 0 ("sqrt.c") 24)
(insn 18 17 19 0 0x1002f390 (set (reg:DF 0 r0 [85])
(reg/v:DF 8 r8 [71])) 10 {*movdf} (insn_list 3 (nil))
(nil))
(note 19 18 20 0 ("sqrt.c") 25)
(insn 20 19 21 0 0x1002f390 (set (reg/v:SI 3 r3 [79])
(reg:SI 1 r1)) 6 {*movsi} (insn_list 18 (nil))
(nil))
(note 21 20 22 0 ("sqrt.c") 26)
(insn 22 21 25 0 0x1002f390 (set (reg/v:SI 12 r12 [77])
(reg:SI 0 r0 [85])) 6 {*movsi} (nil)
(nil))
(note 25 22 589 0 ("sqrt.c") 31)
(insn 589 25 26 0 0x0 (set (reg:SI 0 r0 [86])
(reg/v:SI 3 r3 [79])) 6 {*movsi} (nil)
(nil))
(insn 26 589 27 0 0x1002f450 (set (reg:SI 0 r0 [86])
(and:SI (reg:SI 0 r0 [86])
(const_int 2146435072 [0x7ff00000]))) 25 {andsi3} (insn_list 20 (nil))
(nil))
(insn:QI 27 26 28 0 0x1002f450 (set (cc0)
(compare:SI (reg:SI 0 r0 [86])
(const_int 2146435072 [0x7ff00000]))) 29 {cmpsi_internal} (insn_list 26 (nil))
(nil))
(jump_insn 28 27 31 0 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 53)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 0, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 31 28 452 ("sqrt.c") 33)
;; Start of basic block 1, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71
(note 452 31 34 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(note 34 452 38 1 NOTE_INSN_DELETED)
(insn 38 34 39 1 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 8 r8 [71])) 6 {*movsi} (nil)
(nil))
(insn 39 38 40 1 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 9 r9)) 6 {*movsi} (nil)
(nil))
(call_insn/u 40 39 41 1 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__muldf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 39 (insn_list 38 (nil)))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 41 40 42 1 0x1002f450 (set (reg:DF 18 r18 [91])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 40 (nil))
(expr_list:REG_EQUAL (mult:DF (reg:DF 17 r17)
(reg:DF 17 r17))
(nil)))
(note 42 41 43 1 NOTE_INSN_DELETED)
(insn 43 42 46 1 0x1002f450 (set (reg:DF 17 r17)
(reg:DF 18 r18 [91])) 10 {*movdf} (insn_list 41 (nil))
(nil))
(insn 46 43 47 1 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 8 r8 [71])) 6 {*movsi} (nil)
(nil))
(insn 47 46 48 1 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 9 r9)) 6 {*movsi} (nil)
(nil))
(call_insn/u 48 47 49 1 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__adddf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 47 (insn_list 46 (insn_list 43 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 49 48 51 1 0x1002f450 (set (reg:DF 14 r14 [70])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 48 (nil))
(expr_list:REG_EQUAL (plus:DF (reg:DF 18 r18 [91])
(reg/v:DF 8 r8 [71]))
(nil)))
(jump_insn 51 49 52 1 0x1002f450 (set (pc)
(label_ref 445)) 35 {jump} (nil)
(nil))
;; End of basic block 1, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(barrier 52 51 53)
;; Start of basic block 2, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153
(code_label 53 52 453 2 3 "" [1 uses])
(note 453 53 54 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 54 453 55 2 ("sqrt.c") 37)
(insn:QI 55 54 56 2 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 3 r3 [79])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 56 55 59 2 0x1002f450 (set (pc)
(if_then_else (gt (cc0)
(const_int 0 [0x0]))
(label_ref 109)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7900 [0x1edc])
(nil)))
;; End of basic block 2, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 59 56 454 ("sqrt.c") 39)
;; Start of basic block 3, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153
(note 454 59 590 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 590 454 61 3 0x0 (set (reg:SI 0 r0 [97])
(reg/v:SI 3 r3 [79])) 6 {*movsi} (nil)
(nil))
(insn 61 590 62 3 0x1002f450 (set (reg:SI 0 r0 [97])
(and:SI (reg:SI 0 r0 [97])
(const_int 2147483647 [0x7fffffff]))) 25 {andsi3} (nil)
(nil))
(insn 62 61 68 3 0x1002f450 (set (reg:SI 0 r0 [97])
(ior:SI (reg:SI 0 r0 [97])
(reg/v:SI 12 r12 [77]))) 26 {iorsi3} (insn_list 61 (nil))
(nil))
(insn 68 62 63 3 0x1002f450 (set (reg:DF 14 r14 [70])
(reg/v:DF 8 r8 [71])) 10 {*movdf} (nil)
(nil))
(insn:QI 63 68 64 3 0x1002f450 (set (cc0)
(compare:SI (reg:SI 0 r0 [97])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 62 (nil))
(nil))
(jump_insn 64 63 65 3 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 445)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 3, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 71 77 79 153
(note 65 64 457 ("sqrt.c") 40)
;; Start of basic block 5, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71 77 79 153
(note 457 65 74 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note 74 457 75 5 ("sqrt.c") 41)
(insn:QI 75 74 76 5 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 3 r3 [79])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 76 75 77 5 0x1002f450 (set (pc)
(if_then_else (ge (cc0)
(const_int 0 [0x0]))
(label_ref 109)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7900 [0x1edc])
(nil)))
;; End of basic block 5, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 77 76 458 ("sqrt.c") 42)
;; Start of basic block 6, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 71
(note 458 77 80 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 80 458 84 6 0x1002f450 (set (reg/f:SI 6 r6 [101])
(symbol_ref:SI ("__subdf3"))) 6 {*movsi} (nil)
(expr_list:REG_EQUIV (symbol_ref:SI ("__subdf3"))
(nil)))
(insn 84 80 85 6 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 8 r8 [71])) 6 {*movsi} (nil)
(nil))
(insn 85 84 86 6 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 9 r9)) 6 {*movsi} (nil)
(nil))
(call_insn/u 86 85 87 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (reg/f:SI 6 r6 [101]) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 80 (insn_list 84 (insn_list 85 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 87 86 89 6 0x1002f450 (set (reg:DF 4 r4 [104])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 86 (nil))
(expr_list:REG_EQUAL (minus:DF (reg:DF 17 r17)
(reg:DF 17 r17))
(nil)))
(insn 89 87 92 6 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 8 r8 [71])) 10 {*movdf} (nil)
(nil))
(insn 92 89 93 6 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 17 r17)) 6 {*movsi} (nil)
(nil))
(insn 93 92 94 6 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 18 r18)) 6 {*movsi} (nil)
(nil))
(call_insn/u 94 93 95 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (reg/f:SI 6 r6 [101]) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 89 (insn_list 92 (insn_list 93 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 95 94 96 6 0x1002f450 (set (reg:DF 0 r0 [108])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 94 (nil))
(expr_list:REG_EQUAL (minus:DF (reg/v:DF 8 r8 [71])
(reg/v:DF 8 r8 [71]))
(nil)))
(note 96 95 97 6 NOTE_INSN_DELETED)
(insn 97 96 100 6 0x1002f450 (set (reg:DF 17 r17)
(reg:DF 4 r4 [104])) 10 {*movdf} (insn_list 87 (nil))
(nil))
(insn 100 97 101 6 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 0 r0 [108])) 6 {*movsi} (insn_list 95 (nil))
(nil))
(insn 101 100 102 6 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 1 r1)) 6 {*movsi} (nil)
(nil))
(call_insn/u 102 101 103 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__divdf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 101 (insn_list 100 (insn_list 97 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 103 102 105 6 0x1002f450 (set (reg:DF 14 r14 [70])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 102 (nil))
(expr_list:REG_EQUAL (div:DF (reg:DF 4 r4 [104])
(reg:DF 0 r0 [108]))
(nil)))
(jump_insn 105 103 106 6 0x1002f450 (set (pc)
(label_ref 445)) 35 {jump} (nil)
(nil))
;; End of basic block 6, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(barrier 106 105 109)
;; Start of basic block 7, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 153
(code_label 109 106 461 7 4 "" [2 uses])
(note 461 109 110 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(note 110 461 591 7 ("sqrt.c") 45)
(insn 591 110 111 7 0x0 (set (reg/v:SI 4 r4 [82])
(reg/v:SI 3 r3 [79])) 6 {*movsi} (nil)
(nil))
(insn 111 591 112 7 0x1002f450 (set (reg/v:SI 4 r4 [82])
(ashiftrt:SI (reg/v:SI 4 r4 [82])
(const_int 20 [0x14]))) 23 {ashrsi3} (nil)
(nil))
(note 112 111 113 7 ("sqrt.c") 46)
(insn:QI 113 112 114 7 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 4 r4 [82])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 111 (nil))
(nil))
(jump_insn 114 113 117 7 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 177)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 7, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 117 114 550 ("sqrt.c") 48)
;; Start of basic block 8, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(note 550 117 521 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn:QI 521 550 522 8 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 3 r3 [79])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 522 521 118 8 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 523)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 8, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 118 522 136 NOTE_INSN_LOOP_BEG)
;; Start of basic block 9, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(code_label 136 118 463 9 12 "" [1 uses])
(note 463 136 128 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(note 128 463 129 9 ("sqrt.c") 50)
(insn 129 128 130 9 0x1002f450 (set (reg/v:SI 4 r4 [82])
(plus:SI (reg/v:SI 4 r4 [82])
(const_int -21 [0xffffffeb]))) 12 {addsi3} (nil)
(nil))
(note 130 129 592 9 ("sqrt.c") 51)
(insn 592 130 131 9 0x0 (set (reg:SI 0 r0 [113])
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 131 592 132 9 0x1002f450 (set (reg:SI 0 r0 [113])
(lshiftrt:SI (reg:SI 0 r0 [113])
(const_int 11 [0xb]))) 24 {lshrsi3} (nil)
(nil))
(insn 132 131 133 9 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ior:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [113]))) 26 {iorsi3} (insn_list 131 (nil))
(nil))
(note 133 132 134 9 ("sqrt.c") 52)
(insn 134 133 135 9 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(const_int 21 [0x15]))) 22 {ashlsi3} (nil)
(nil))
(note 135 134 527 9 NOTE_INSN_LOOP_CONT)
(note 527 135 120 9 NOTE_INSN_LOOP_VTOP)
(insn:QI 120 527 121 9 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 3 r3 [79])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 132 (nil))
(nil))
(jump_insn 121 120 141 9 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 136)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 9, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 141 121 523 NOTE_INSN_LOOP_END)
;; Start of basic block 10, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(code_label 523 141 467 10 46 "" [1 uses])
(note 467 523 143 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(note 143 467 144 10 ("sqrt.c") 54)
(insn 144 143 593 10 0x1002f450 (set (reg/v:SI 1 r1 [84])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 593 144 528 10 0x0 (set (reg:SI 0 r0 [155])
(reg/v:SI 3 r3 [79])) 6 {*movsi} (nil)
(nil))
(insn 528 593 529 10 0x1002f450 (set (reg:SI 0 r0 [155])
(and:SI (reg:SI 0 r0 [155])
(const_int 1048576 [0x100000]))) 25 {andsi3} (nil)
(nil))
(insn:QI 529 528 530 10 0x1002f450 (set (cc0)
(compare:SI (reg:SI 0 r0 [155])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 528 (nil))
(nil))
(jump_insn 530 529 145 10 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 531)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 10, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(note 145 530 160 NOTE_INSN_LOOP_BEG)
;; Start of basic block 11, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 84 153
(code_label 160 145 468 11 17 "" [1 uses])
(note 468 160 154 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(note 154 468 155 11 ("sqrt.c") 55)
(insn 155 154 156 11 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ashift:SI (reg/v:SI 3 r3 [79])
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 156 155 157 11 ("sqrt.c") 54)
(note 157 156 159 11 NOTE_INSN_LOOP_CONT)
(insn 159 157 535 11 0x1002f450 (set (reg/v:SI 1 r1 [84])
(plus:SI (reg/v:SI 1 r1 [84])
(const_int 1 [0x1]))) 12 {addsi3} (nil)
(nil))
(note 535 159 594 11 NOTE_INSN_LOOP_VTOP)
(insn 594 535 147 11 0x0 (set (reg/s:SI 0 r0 [114])
(reg/v:SI 3 r3 [79])) 6 {*movsi} (nil)
(nil))
(insn 147 594 148 11 0x1002f450 (set (reg/s:SI 0 r0 [114])
(and:SI (reg/s:SI 0 r0 [114])
(const_int 1048576 [0x100000]))) 25 {andsi3} (insn_list 155 (nil))
(nil))
(insn:QI 148 147 149 11 0x1002f450 (set (cc0)
(compare:SI (reg/s:SI 0 r0 [114])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 147 (nil))
(nil))
(jump_insn 149 148 165 11 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 160)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 11, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(note 165 149 531 NOTE_INSN_LOOP_END)
;; Start of basic block 12, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 84 153
(code_label 531 165 473 12 48 "" [1 uses])
(note 473 531 167 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(note 167 473 595 12 ("sqrt.c") 56)
(insn 595 167 168 12 0x0 (set (reg:SI 0 r0 [115])
(reg/v:SI 4 r4 [82])) 6 {*movsi} (nil)
(nil))
(insn 168 595 169 12 0x1002f450 (set (reg:SI 0 r0 [115])
(minus:SI (reg:SI 0 r0 [115])
(reg/v:SI 1 r1 [84]))) 13 {subsi3} (nil)
(nil))
(insn 169 168 170 12 0x1002f450 (set (reg/v:SI 4 r4 [82])
(plus:SI (reg:SI 0 r0 [115])
(const_int 1 [0x1]))) 12 {addsi3} (insn_list 168 (nil))
(nil))
(note 170 169 171 12 ("sqrt.c") 57)
(note 171 170 596 12 NOTE_INSN_DELETED)
(insn 596 171 172 12 0x0 (set (reg:SI 0 r0 [116])
(reg/v:SI 1 r1 [84])) 6 {*movsi} (nil)
(nil))
(insn 172 596 597 12 0x1002f450 (set (reg:SI 0 r0 [116])
(neg:SI (reg:SI 0 r0 [116]))) 15 {negsi2} (nil)
(nil))
(insn 597 172 173 12 0x0 (set (reg:SI 2 r2)
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 173 597 598 12 0x1002f450 (set (reg:SI 2 r2)
(lshiftrt:SI (reg:SI 2 r2)
(reg:SI 0 r0 [116]))) 24 {lshrsi3} (insn_list 172 (nil))
(nil))
(insn 598 173 174 12 0x0 (set (reg:SI 0 r0 [118])
(reg:SI 2 r2)) 6 {*movsi} (nil)
(nil))
(insn 174 598 175 12 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ior:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [118]))) 26 {iorsi3} (insn_list 173 (nil))
(nil))
(note 175 174 176 12 ("sqrt.c") 58)
(insn 176 175 177 12 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(reg/v:SI 1 r1 [84]))) 22 {ashlsi3} (nil)
(nil))
;; End of basic block 12, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 13, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(code_label 177 176 474 13 8 "" [1 uses])
(note 474 177 178 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(note 178 474 179 13 ("sqrt.c") 60)
(insn 179 178 180 13 0x1002f450 (set (reg/v:SI 4 r4 [82])
(plus:SI (reg/v:SI 4 r4 [82])
(const_int -1023 [0xfffffc01]))) 12 {addsi3} (nil)
(nil))
(note 180 179 181 13 ("sqrt.c") 61)
(insn 181 180 182 13 0x1002f450 (set (reg/v:SI 3 r3 [79])
(and:SI (reg/v:SI 3 r3 [79])
(const_int 1048575 [0xfffff]))) 25 {andsi3} (nil)
(nil))
(insn 182 181 183 13 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ior:SI (reg/v:SI 3 r3 [79])
(const_int 1048576 [0x100000]))) 26 {iorsi3} (insn_list 181 (nil))
(nil))
(note 183 182 599 13 ("sqrt.c") 62)
(insn 599 183 184 13 0x0 (set (reg:SI 0 r0 [120])
(reg/v:SI 4 r4 [82])) 6 {*movsi} (nil)
(nil))
(insn 184 599 185 13 0x1002f450 (set (reg:SI 0 r0 [120])
(and:SI (reg:SI 0 r0 [120])
(const_int 1 [0x1]))) 25 {andsi3} (insn_list 179 (nil))
(nil))
(insn:QI 185 184 186 13 0x1002f450 (set (cc0)
(compare:SI (reg:SI 0 r0 [120])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 184 (nil))
(nil))
(jump_insn 186 185 189 13 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 196)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 13, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 189 186 475 ("sqrt.c") 64)
;; Start of basic block 14, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(note 475 189 190 14 [bb 14] NOTE_INSN_BASIC_BLOCK)
(note 190 475 600 14 NOTE_INSN_DELETED)
(insn 600 190 191 14 0x0 (set (reg:SI 0 r0 [122])
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 191 600 192 14 0x1002f450 (set (reg:SI 0 r0 [122])
(lshiftrt:SI (reg:SI 0 r0 [122])
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 192 191 193 14 0x1002f450 (set (reg:SI 0 r0 [123])
(plus:SI (reg:SI 0 r0 [122])
(reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 191 (nil))
(nil))
(insn 193 192 194 14 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [123]))) 12 {addsi3} (insn_list 192 (nil))
(nil))
(note 194 193 195 14 ("sqrt.c") 65)
(insn 195 194 196 14 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
;; End of basic block 14, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 15, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(code_label 196 195 476 15 18 "" [1 uses])
(note 476 196 197 15 [bb 15] NOTE_INSN_BASIC_BLOCK)
(note 197 476 198 15 ("sqrt.c") 67)
(insn 198 197 199 15 0x1002f450 (set (reg/v:SI 4 r4 [82])
(ashiftrt:SI (reg/v:SI 4 r4 [82])
(const_int 1 [0x1]))) 23 {ashrsi3} (nil)
(nil))
(note 199 198 200 15 ("sqrt.c") 70)
(note 200 199 601 15 NOTE_INSN_DELETED)
(insn 601 200 201 15 0x0 (set (reg:SI 0 r0 [125])
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 201 601 202 15 0x1002f450 (set (reg:SI 0 r0 [125])
(lshiftrt:SI (reg:SI 0 r0 [125])
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 202 201 203 15 0x1002f450 (set (reg:SI 0 r0 [126])
(plus:SI (reg:SI 0 r0 [125])
(reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 201 (nil))
(nil))
(insn 203 202 204 15 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [126]))) 12 {addsi3} (insn_list 202 (nil))
(nil))
(note 204 203 205 15 ("sqrt.c") 71)
(insn 205 204 206 15 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 206 205 207 15 ("sqrt.c") 72)
(insn 207 206 208 15 0x1002f450 (set (reg/v:SI 17 r17 [76])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 208 207 209 15 0x1002f450 (set (reg/v:SI 15 r15 [80])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 209 208 210 15 0x1002f450 (set (reg/v:SI 8 r8 [78])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 210 209 211 15 0x1002f450 (set (reg/v:SI 6 r6 [81])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(note 211 210 212 15 ("sqrt.c") 73)
(insn 212 211 213 15 0x1002f450 (set (reg/v:SI 13 r13 [74])
(const_int 2097152 [0x200000])) 6 {*movsi} (nil)
(nil))
;; End of basic block 15, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 213 212 214 ("sqrt.c") 75)
(note 214 213 248 NOTE_INSN_LOOP_BEG)
;; Start of basic block 16, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153
(code_label 248 214 477 16 23 "" [1 uses])
(note 477 248 224 16 [bb 16] NOTE_INSN_BASIC_BLOCK)
(note 224 477 602 16 ("sqrt.c") 77)
(insn 602 224 225 16 0x0 (set (reg/v:SI 2 r2 [83])
(reg/v:SI 15 r15 [80])) 6 {*movsi} (nil)
(nil))
(insn 225 602 226 16 0x1002f450 (set (reg/v:SI 2 r2 [83])
(plus:SI (reg/v:SI 2 r2 [83])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
(note 226 225 227 16 ("sqrt.c") 78)
(insn:QI 227 226 228 16 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 2 r2 [83])
(reg/v:SI 3 r3 [79]))) 29 {cmpsi_internal} (insn_list 225 (nil))
(nil))
(jump_insn 228 227 231 16 0x1002f450 (set (pc)
(if_then_else (gt (cc0)
(const_int 0 [0x0]))
(label_ref 237)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 16, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 83 153
(note 231 228 478 ("sqrt.c") 80)
;; Start of basic block 17, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 81 82 83 153
(note 478 231 603 17 [bb 17] NOTE_INSN_BASIC_BLOCK)
(insn 603 478 232 17 0x0 (set (reg/v:SI 15 r15 [80])
(reg/v:SI 2 r2 [83])) 6 {*movsi} (nil)
(nil))
(insn 232 603 233 17 0x1002f450 (set (reg/v:SI 15 r15 [80])
(plus:SI (reg/v:SI 15 r15 [80])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
(note 233 232 234 17 ("sqrt.c") 81)
(insn 234 233 235 17 0x1002f450 (set (reg/v:SI 3 r3 [79])
(minus:SI (reg/v:SI 3 r3 [79])
(reg/v:SI 2 r2 [83]))) 13 {subsi3} (nil)
(nil))
(note 235 234 236 17 ("sqrt.c") 82)
(insn 236 235 237 17 0x1002f450 (set (reg/v:SI 6 r6 [81])
(plus:SI (reg/v:SI 6 r6 [81])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
;; End of basic block 17, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
;; Start of basic block 18, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153
(code_label 237 236 479 18 22 "" [1 uses])
(note 479 237 238 18 [bb 18] NOTE_INSN_BASIC_BLOCK)
(note 238 479 239 18 ("sqrt.c") 84)
(note 239 238 604 18 NOTE_INSN_DELETED)
(insn 604 239 240 18 0x0 (set (reg:SI 0 r0 [128])
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 240 604 241 18 0x1002f450 (set (reg:SI 0 r0 [128])
(lshiftrt:SI (reg:SI 0 r0 [128])
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 241 240 242 18 0x1002f450 (set (reg:SI 0 r0 [129])
(plus:SI (reg:SI 0 r0 [128])
(reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 240 (nil))
(nil))
(insn 242 241 243 18 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [129]))) 12 {addsi3} (insn_list 241 (nil))
(nil))
(note 243 242 244 18 ("sqrt.c") 85)
(insn 244 243 245 18 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 245 244 246 18 ("sqrt.c") 86)
(insn 246 245 247 18 0x1002f450 (set (reg/v:SI 13 r13 [74])
(lshiftrt:SI (reg/v:SI 13 r13 [74])
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(nil))
(note 247 246 542 18 NOTE_INSN_LOOP_CONT)
(note 542 247 216 18 NOTE_INSN_LOOP_VTOP)
(insn:QI 216 542 217 18 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 13 r13 [74])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 246 (nil))
(nil))
(jump_insn 217 216 253 18 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 248)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 18, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 253 217 255 NOTE_INSN_LOOP_END)
(note 255 253 483 ("sqrt.c") 89)
;; Start of basic block 19, registers live: 20 [r20] 21 [r21] 30 [r30] 76 77 78 79 80 81 82 153
(note 483 255 256 19 [bb 19] NOTE_INSN_BASIC_BLOCK)
(insn 256 483 257 19 0x1002f450 (set (reg/v:SI 13 r13 [74])
(const_int -2147483648 [0x80000000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int -2147483648 [0x80000000])
(nil)))
(note 257 256 585 19 ("sqrt.c") 90)
(insn 585 257 543 19 0x0 (set (reg/v:SI 0 r0 [73])
(const_int -2147483648 [0x80000000])) 6 {*movsi} (nil)
(expr_list:REG_EQUIV (const_int -2147483648 [0x80000000])
(nil)))
(insn:QI 543 585 544 19 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 0 r0 [73])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(expr_list:REG_EQUAL (compare:SI (const_int -2147483648 [0x80000000])
(const_int 0 [0x0]))
(nil)))
(jump_insn 544 543 258 19 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 545)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 19, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 258 544 328 NOTE_INSN_LOOP_BEG)
;; Start of basic block 20, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153
(code_label 328 258 484 20 33 "" [1 uses])
(note 484 328 268 20 [bb 20] NOTE_INSN_BASIC_BLOCK)
(note 268 484 605 20 ("sqrt.c") 92)
(insn 605 268 269 20 0x0 (set (reg/v:SI 14 r14 [75])
(reg/v:SI 17 r17 [76])) 6 {*movsi} (nil)
(nil))
(insn 269 605 270 20 0x1002f450 (set (reg/v:SI 14 r14 [75])
(plus:SI (reg/v:SI 14 r14 [75])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
(note 270 269 271 20 ("sqrt.c") 93)
(insn 271 270 272 20 0x1002f450 (set (reg/v:SI 2 r2 [83])
(reg/v:SI 15 r15 [80])) 6 {*movsi} (nil)
(nil))
(note 272 271 273 20 ("sqrt.c") 94)
(insn:QI 273 272 274 20 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 2 r2 [83])
(reg/v:SI 3 r3 [79]))) 29 {cmpsi_internal} (insn_list 271 (nil))
(nil))
(jump_insn 274 273 485 20 0x1002f450 (set (pc)
(if_then_else (lt (cc0)
(const_int 0 [0x0]))
(label_ref 290)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 20, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 21, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153
(note 485 274 606 21 [bb 21] NOTE_INSN_BASIC_BLOCK)
(insn 606 485 562 21 0x0 (set (reg:SI 0 r0 [164])
(reg/v:SI 2 r2 [83])) 6 {*movsi} (nil)
(nil))
(insn 562 606 607 21 0x1002f450 (set (reg:SI 0 r0 [164])
(xor:SI (reg:SI 0 r0 [164])
(reg/v:SI 3 r3 [79]))) 27 {xorsi3} (nil)
(nil))
(insn 607 562 563 21 0x0 (set (reg:SI 1 r1 [168])
(reg:SI 0 r0 [164])) 6 {*movsi} (nil)
(nil))
(insn 563 607 564 21 0x1002f450 (set (reg:SI 1 r1 [168])
(neg:SI (reg:SI 1 r1 [168]))) 15 {negsi2} (insn_list 562 (nil))
(nil))
(insn 564 563 565 21 0x1002f450 (set (reg:SI 1 r1 [168])
(ior:SI (reg:SI 1 r1 [168])
(reg:SI 0 r0 [164]))) 26 {iorsi3} (insn_list 563 (nil))
(nil))
(insn 565 564 566 21 0x1002f450 (set (reg:SI 1 r1 [168])
(not:SI (reg:SI 1 r1 [168]))) 28 {one_cmplsi2} (insn_list 564 (nil))
(nil))
(note 566 565 567 21 NOTE_INSN_DELETED)
(insn 567 566 280 21 0x1002f450 (set (reg:SI 1 r1 [168])
(lshiftrt:SI (reg:SI 1 r1 [168])
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 565 (nil))
(nil))
(insn 280 567 281 21 0x1002f450 (set (reg:SI 0 r0 [131])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn:QI 281 280 282 21 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 12 r12 [77])
(reg/v:SI 14 r14 [75]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 282 281 488 21 0x1002f450 (set (pc)
(if_then_else (ltu (cc0)
(const_int 0 [0x0]))
(label_ref 284)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 21, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
;; Start of basic block 22, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153 168
(note 488 282 283 22 [bb 22] NOTE_INSN_BASIC_BLOCK)
(insn 283 488 284 22 0x1002f450 (set (reg:SI 0 r0 [131])
(const_int 1 [0x1])) 6 {*movsi} (nil)
(insn_list:REG_WAS_0 280 (expr_list:REG_EQUAL (const_int 1 [0x1])
(nil))))
;; End of basic block 22, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
;; Start of basic block 23, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 131 153 168
(code_label 284 283 489 23 30 "" [1 uses])
(note 489 284 285 23 [bb 23] NOTE_INSN_BASIC_BLOCK)
(insn 285 489 286 23 0x1002f450 (set (reg:SI 1 r1 [168])
(and:SI (reg:SI 1 r1 [168])
(reg:SI 0 r0 [131]))) 25 {andsi3} (nil)
(nil))
(insn:QI 286 285 287 23 0x1002f450 (set (cc0)
(compare:SI (reg:SI 1 r1 [168])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 285 (nil))
(nil))
(jump_insn 287 286 290 23 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 317)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 23, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 24, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 77 78 79 80 81 82 83 153
(code_label 290 287 491 24 28 "" [1 uses])
(note 491 290 293 24 [bb 24] NOTE_INSN_BASIC_BLOCK)
(note 293 491 608 24 ("sqrt.c") 96)
(insn 608 293 294 24 0x0 (set (reg/v:SI 17 r17 [76])
(reg/v:SI 14 r14 [75])) 6 {*movsi} (nil)
(nil))
(insn 294 608 295 24 0x1002f450 (set (reg/v:SI 17 r17 [76])
(plus:SI (reg/v:SI 17 r17 [76])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
(note 295 294 609 24 ("sqrt.c") 97)
(insn 609 295 296 24 0x0 (set (reg:SI 0 r0 [133])
(reg/v:SI 14 r14 [75])) 6 {*movsi} (nil)
(nil))
(insn 296 609 297 24 0x1002f450 (set (reg:SI 0 r0 [133])
(and:SI (reg:SI 0 r0 [133])
(const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil)
(nil))
(insn:QI 297 296 298 24 0x1002f450 (set (cc0)
(compare:SI (reg:SI 0 r0 [133])
(const_int -2147483648 [0x80000000]))) 29 {cmpsi_internal} (insn_list 296 (nil))
(nil))
(jump_insn 298 297 492 24 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 304)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 24, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 25, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153
(note 492 298 610 25 [bb 25] NOTE_INSN_BASIC_BLOCK)
(insn 610 492 299 25 0x0 (set (reg:SI 1 r1 [134])
(reg/v:SI 17 r17 [76])) 6 {*movsi} (nil)
(nil))
(insn 299 610 611 25 0x1002f450 (set (reg:SI 1 r1 [134])
(and:SI (reg:SI 1 r1 [134])
(const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil)
(nil))
(insn 611 299 568 25 0x0 (set (reg:SI 0 r0 [170])
(reg:SI 1 r1 [134])) 6 {*movsi} (nil)
(nil))
(insn 568 611 569 25 0x1002f450 (set (reg:SI 0 r0 [170])
(neg:SI (reg:SI 0 r0 [170]))) 15 {negsi2} (insn_list 299 (nil))
(nil))
(insn 569 568 570 25 0x1002f450 (set (reg:SI 0 r0 [170])
(ior:SI (reg:SI 0 r0 [170])
(reg:SI 1 r1 [134]))) 26 {iorsi3} (insn_list 568 (nil))
(nil))
(insn 570 569 571 25 0x1002f450 (set (reg:SI 0 r0 [170])
(not:SI (reg:SI 0 r0 [170]))) 28 {one_cmplsi2} (insn_list 569 (nil))
(nil))
(insn 571 570 573 25 0x1002f450 (set (reg:SI 0 r0 [170])
(lshiftrt:SI (reg:SI 0 r0 [170])
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 570 (nil))
(nil))
(insn 573 571 302 25 0x1002f450 (set (reg/v:SI 15 r15 [80])
(plus:SI (reg/v:SI 15 r15 [80])
(reg:SI 0 r0 [170]))) 12 {addsi3} (insn_list 571 (nil))
(nil))
;; End of basic block 25, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
(note 302 573 304 ("sqrt.c") 98)
;; Start of basic block 26, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 83 153
(code_label 304 302 494 26 31 "" [1 uses])
(note 494 304 305 26 [bb 26] NOTE_INSN_BASIC_BLOCK)
(note 305 494 306 26 ("sqrt.c") 99)
(insn 306 305 307 26 0x1002f450 (set (reg/v:SI 3 r3 [79])
(minus:SI (reg/v:SI 3 r3 [79])
(reg/v:SI 2 r2 [83]))) 13 {subsi3} (nil)
(nil))
(note 307 306 308 26 ("sqrt.c") 100)
(insn:QI 308 307 309 26 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 12 r12 [77])
(reg/v:SI 14 r14 [75]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 309 308 310 26 0x1002f450 (set (pc)
(if_then_else (geu (cc0)
(const_int 0 [0x0]))
(label_ref 312)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 26, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
(note 310 309 495 ("sqrt.c") 101)
;; Start of basic block 27, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 153
(note 495 310 311 27 [bb 27] NOTE_INSN_BASIC_BLOCK)
(insn 311 495 312 27 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(const_int -1 [0xffffffff]))) 12 {addsi3} (nil)
(nil))
;; End of basic block 27, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
;; Start of basic block 28, registers live: 20 [r20] 21 [r21] 30 [r30] 74 75 76 77 78 79 80 81 82 153
(code_label 312 311 496 28 32 "" [1 uses])
(note 496 312 313 28 [bb 28] NOTE_INSN_BASIC_BLOCK)
(note 313 496 314 28 ("sqrt.c") 102)
(insn 314 313 315 28 0x1002f450 (set (reg/v:SI 12 r12 [77])
(minus:SI (reg/v:SI 12 r12 [77])
(reg/v:SI 14 r14 [75]))) 13 {subsi3} (nil)
(nil))
(note 315 314 316 28 ("sqrt.c") 103)
(insn 316 315 317 28 0x1002f450 (set (reg/v:SI 8 r8 [78])
(plus:SI (reg/v:SI 8 r8 [78])
(reg/v:SI 13 r13 [74]))) 12 {addsi3} (nil)
(nil))
;; End of basic block 28, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
;; Start of basic block 29, registers live: 20 [r20] 21 [r21] 30 [r30] 74 76 77 78 79 80 81 82 153
(code_label 317 316 497 29 27 "" [1 uses])
(note 497 317 318 29 [bb 29] NOTE_INSN_BASIC_BLOCK)
(note 318 497 319 29 ("sqrt.c") 105)
(note 319 318 612 29 NOTE_INSN_DELETED)
(insn 612 319 320 29 0x0 (set (reg:SI 0 r0 [136])
(reg/v:SI 12 r12 [77])) 6 {*movsi} (nil)
(nil))
(insn 320 612 321 29 0x1002f450 (set (reg:SI 0 r0 [136])
(lshiftrt:SI (reg:SI 0 r0 [136])
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 321 320 322 29 0x1002f450 (set (reg:SI 0 r0 [137])
(plus:SI (reg:SI 0 r0 [136])
(reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 320 (nil))
(nil))
(insn 322 321 323 29 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(reg:SI 0 r0 [137]))) 12 {addsi3} (insn_list 321 (nil))
(nil))
(note 323 322 324 29 ("sqrt.c") 106)
(insn 324 323 325 29 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ashift:SI (reg/v:SI 12 r12 [77])
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 325 324 326 29 ("sqrt.c") 107)
(insn 326 325 327 29 0x1002f450 (set (reg/v:SI 13 r13 [74])
(lshiftrt:SI (reg/v:SI 13 r13 [74])
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(nil))
(note 327 326 549 29 NOTE_INSN_LOOP_CONT)
(note 549 327 260 29 NOTE_INSN_LOOP_VTOP)
(insn:QI 260 549 261 29 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 13 r13 [74])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 326 (nil))
(nil))
(jump_insn 261 260 333 29 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 328)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 29, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 333 261 545 NOTE_INSN_LOOP_END)
;; Start of basic block 30, registers live: 20 [r20] 21 [r21] 30 [r30] 77 78 79 81 82 153
(code_label 545 333 501 30 52 "" [1 uses])
(note 501 545 335 30 [bb 30] NOTE_INSN_BASIC_BLOCK)
(note 335 501 336 30 ("sqrt.c") 111)
(insn 336 335 337 30 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ior:SI (reg/v:SI 3 r3 [79])
(reg/v:SI 12 r12 [77]))) 26 {iorsi3} (nil)
(nil))
(insn:QI 337 336 338 30 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 3 r3 [79])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 336 (nil))
(nil))
(jump_insn 338 337 341 30 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 408)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 30, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 341 338 502 ("sqrt.c") 113)
;; Start of basic block 31, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153
(note 502 341 342 31 [bb 31] NOTE_INSN_BASIC_BLOCK)
(insn 342 502 343 31 0x1002f450 (set (reg/v:DF 10 r10 [72])
(mem/u/f:DF (symbol_ref/u:SI ("*.LC0")) [2 S8 A32])) 10 {*movdf} (nil)
(expr_list:REG_EQUIV (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(nil)))
(note 343 342 344 31 ("sqrt.c") 114)
(note 344 343 345 31 NOTE_INSN_DELETED)
(insn 345 344 349 31 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 10 r10 [72])) 10 {*movdf} (insn_list 342 (nil))
(expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(nil)))
(insn 349 345 350 31 0x1002f450 (set (reg:SI 19 r19)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 350 349 351 31 0x1002f450 (set (reg:SI 0 r0)
(const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000])
(nil)))
(call_insn/u 351 350 352 31 0x1002f450 (parallel [
(set (reg:SI 18 r18)
(call (mem:QI (symbol_ref:SI ("__gedf2")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 350 (insn_list 349 (insn_list 345 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 352 351 353 31 0x1002f450 (set (reg:SI 18 r18 [143])
(reg:SI 18 r18)) 6 {*movsi} (insn_list 351 (nil))
(expr_list:REG_EQUAL (expr_list (reg/f:SI 139)
(expr_list (reg/v:DF 10 r10 [72])
(expr_list (reg/v:DF 10 r10 [72])
(nil))))
(nil)))
(insn:QI 353 352 354 31 0x1002f450 (set (cc0)
(compare:SI (reg:SI 18 r18 [143])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 352 (nil))
(nil))
(jump_insn 354 353 360 31 0x1002f450 (set (pc)
(if_then_else (lt (cc0)
(const_int 0 [0x0]))
(label_ref 408)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 2100 [0x834])
(nil)))
;; End of basic block 31, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(note 360 354 362 ("sqrt.c") 116)
(note 362 360 504 ("sqrt.c") 117)
;; Start of basic block 32, registers live: 20 [r20] 21 [r21] 30 [r30] 72 78 81 82 153
(note 504 362 363 32 [bb 32] NOTE_INSN_BASIC_BLOCK)
(insn:QI 363 504 364 32 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 8 r8 [78])
(const_int -1 [0xffffffff]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 364 363 367 32 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 373)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 32, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(note 367 364 505 ("sqrt.c") 119)
;; Start of basic block 33, registers live: 20 [r20] 21 [r21] 30 [r30] 81 82 153
(note 505 367 368 33 [bb 33] NOTE_INSN_BASIC_BLOCK)
(insn 368 505 369 33 0x1002f450 (set (reg/v:SI 8 r8 [78])
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(note 369 368 370 33 ("sqrt.c") 120)
(insn 370 369 371 33 0x1002f450 (set (reg/v:SI 6 r6 [81])
(plus:SI (reg/v:SI 6 r6 [81])
(const_int 1 [0x1]))) 12 {addsi3} (nil)
(nil))
(jump_insn 371 370 372 33 0x1002f450 (set (pc)
(label_ref 408)) 35 {jump} (nil)
(nil))
;; End of basic block 33, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(barrier 372 371 373)
;; Start of basic block 34, registers live: 20 [r20] 21 [r21] 30 [r30] 72 78 81 82 153
(code_label 373 372 506 34 37 "" [1 uses])
(note 506 373 374 34 [bb 34] NOTE_INSN_BASIC_BLOCK)
(note 374 506 375 34 ("sqrt.c") 122)
(note 375 374 376 34 NOTE_INSN_DELETED)
(insn 376 375 380 34 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 10 r10 [72])) 10 {*movdf} (nil)
(expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(nil)))
(insn 380 376 381 34 0x1002f450 (set (reg:SI 19 r19)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 381 380 382 34 0x1002f450 (set (reg:SI 0 r0)
(const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000])
(nil)))
(call_insn/u 382 381 383 34 0x1002f450 (parallel [
(set (reg:SI 18 r18)
(call (mem:QI (symbol_ref:SI ("__gtdf2")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 381 (insn_list 380 (insn_list 376 (nil))))
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 383 382 384 34 0x1002f450 (set (reg:SI 18 r18 [148])
(reg:SI 18 r18)) 6 {*movsi} (insn_list 382 (nil))
(expr_list:REG_EQUAL (expr_list (reg/f:SI 144)
(expr_list (reg/v:DF 10 r10 [72])
(expr_list (reg/v:DF 10 r10 [72])
(nil))))
(nil)))
(insn:QI 384 383 385 34 0x1002f450 (set (cc0)
(compare:SI (reg:SI 18 r18 [148])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 383 (nil))
(nil))
(jump_insn 385 384 391 34 0x1002f450 (set (pc)
(if_then_else (le (cc0)
(const_int 0 [0x0]))
(label_ref 401)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 2100 [0x834])
(nil)))
;; End of basic block 34, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 391 385 508 ("sqrt.c") 124)
;; Start of basic block 35, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153
(note 508 391 613 35 [bb 35] NOTE_INSN_BASIC_BLOCK)
(insn 613 508 574 35 0x0 (set (reg:SI 1 r1 [176])
(reg/v:SI 8 r8 [78])) 6 {*movsi} (nil)
(nil))
(insn 574 613 614 35 0x1002f450 (set (reg:SI 1 r1 [176])
(xor:SI (reg:SI 1 r1 [176])
(const_int -2 [0xfffffffe]))) 27 {xorsi3} (nil)
(nil))
(insn 614 574 575 35 0x0 (set (reg:SI 0 r0 [177])
(reg:SI 1 r1 [176])) 6 {*movsi} (nil)
(nil))
(insn 575 614 576 35 0x1002f450 (set (reg:SI 0 r0 [177])
(neg:SI (reg:SI 0 r0 [177]))) 15 {negsi2} (insn_list 574 (nil))
(nil))
(insn 576 575 577 35 0x1002f450 (set (reg:SI 0 r0 [177])
(ior:SI (reg:SI 0 r0 [177])
(reg:SI 1 r1 [176]))) 26 {iorsi3} (insn_list 575 (nil))
(nil))
(insn 577 576 578 35 0x1002f450 (set (reg:SI 0 r0 [177])
(not:SI (reg:SI 0 r0 [177]))) 28 {one_cmplsi2} (insn_list 576 (nil))
(nil))
(insn 578 577 580 35 0x1002f450 (set (reg:SI 0 r0 [177])
(lshiftrt:SI (reg:SI 0 r0 [177])
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 577 (nil))
(nil))
(insn 580 578 394 35 0x1002f450 (set (reg/v:SI 6 r6 [81])
(plus:SI (reg/v:SI 6 r6 [81])
(reg:SI 0 r0 [177]))) 12 {addsi3} (insn_list 578 (nil))
(nil))
(note 394 580 397 35 ("sqrt.c") 125)
(note 397 394 398 35 ("sqrt.c") 126)
(insn 398 397 399 35 0x1002f450 (set (reg/v:SI 8 r8 [78])
(plus:SI (reg/v:SI 8 r8 [78])
(const_int 2 [0x2]))) 12 {addsi3} (nil)
(nil))
(jump_insn 399 398 400 35 0x1002f450 (set (pc)
(label_ref 408)) 35 {jump} (nil)
(nil))
;; End of basic block 35, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(barrier 400 399 401)
;; Start of basic block 36, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153
(code_label 401 400 511 36 39 "" [1 uses])
(note 511 401 402 36 [bb 36] NOTE_INSN_BASIC_BLOCK)
(note 402 511 615 36 ("sqrt.c") 129)
(insn 615 402 403 36 0x0 (set (reg:SI 0 r0 [149])
(reg/v:SI 8 r8 [78])) 6 {*movsi} (nil)
(nil))
(insn 403 615 404 36 0x1002f450 (set (reg:SI 0 r0 [149])
(and:SI (reg:SI 0 r0 [149])
(const_int 1 [0x1]))) 25 {andsi3} (nil)
(nil))
(insn 404 403 408 36 0x1002f450 (set (reg/v:SI 8 r8 [78])
(plus:SI (reg/v:SI 8 r8 [78])
(reg:SI 0 r0 [149]))) 12 {addsi3} (insn_list 403 (nil))
(nil))
;; End of basic block 36, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
;; Start of basic block 37, registers live: 20 [r20] 21 [r21] 30 [r30] 78 81 82 153
(code_label 408 404 515 37 34 "" [4 uses])
(note 515 408 409 37 [bb 37] NOTE_INSN_BASIC_BLOCK)
(note 409 515 616 37 ("sqrt.c") 132)
(insn 616 409 410 37 0x0 (set (reg/v:SI 3 r3 [79])
(reg/v:SI 6 r6 [81])) 6 {*movsi} (nil)
(nil))
(insn 410 616 411 37 0x1002f450 (set (reg/v:SI 3 r3 [79])
(ashiftrt:SI (reg/v:SI 3 r3 [79])
(const_int 1 [0x1]))) 23 {ashrsi3} (nil)
(nil))
(insn 411 410 412 37 0x1002f450 (set (reg/v:SI 3 r3 [79])
(plus:SI (reg/v:SI 3 r3 [79])
(const_int 1071644672 [0x3fe00000]))) 12 {addsi3} (insn_list 410 (nil))
(nil))
(note 412 411 617 37 ("sqrt.c") 133)
(insn 617 412 413 37 0x0 (set (reg/v:SI 12 r12 [77])
(reg/v:SI 8 r8 [78])) 6 {*movsi} (nil)
(nil))
(insn 413 617 414 37 0x1002f450 (set (reg/v:SI 12 r12 [77])
(lshiftrt:SI (reg/v:SI 12 r12 [77])
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(nil))
(note 414 413 415 37 ("sqrt.c") 134)
(insn 415 414 416 37 0x1002f450 (set (reg/v:SI 6 r6 [81])
(and:SI (reg/v:SI 6 r6 [81])
(const_int 1 [0x1]))) 25 {andsi3} (nil)
(nil))
(insn:QI 416 415 417 37 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 6 r6 [81])
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 415 (nil))
(nil))
(jump_insn 417 416 418 37 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 420)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 37, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 418 417 516 ("sqrt.c") 135)
;; Start of basic block 38, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(note 516 418 419 38 [bb 38] NOTE_INSN_BASIC_BLOCK)
(insn 419 516 420 38 0x1002f450 (set (reg/v:SI 12 r12 [77])
(ior:SI (reg/v:SI 12 r12 [77])
(const_int -2147483648 [0x80000000]))) 26 {iorsi3} (nil)
(nil))
;; End of basic block 38, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 39, registers live: 20 [r20] 21 [r21] 30 [r30] 77 79 82 153
(code_label 420 419 517 39 43 "" [1 uses])
(note 517 420 421 39 [bb 39] NOTE_INSN_BASIC_BLOCK)
(note 421 517 422 39 ("sqrt.c") 136)
(insn 422 421 423 39 0x1002f450 (set (reg/v:SI 4 r4 [82])
(ashift:SI (reg/v:SI 4 r4 [82])
(const_int 20 [0x14]))) 22 {ashlsi3} (nil)
(nil))
(note 423 422 427 39 NOTE_INSN_DELETED)
(note 427 423 428 39 ("sqrt.c") 139)
(note 428 427 429 39 ("sqrt.c") 140)
(insn 429 428 618 39 0x1002f420 (set (reg/v:SI 4 r4 [82])
(plus:SI (reg/v:SI 4 r4 [82])
(reg/v:SI 3 r3 [79]))) 12 {addsi3} (insn_list 422 (nil))
(nil))
(insn 618 429 619 39 0x0 (set (reg:SI 0 r0)
(reg/v:SI 4 r4 [82])) 6 {*movsi} (nil)
(nil))
(insn 619 618 430 39 0x0 (set (mem:SI (plus:SI (reg/f:SI 21 r21)
(const_int -4 [0xfffffffc])) [3 iw_u S4 A32])
(reg:SI 0 r0)) 6 {*movsi} (nil)
(nil))
(note 430 619 431 39 ("sqrt.c") 141)
(insn 431 430 620 39 0x1002f420 (set (reg:SI 0 r0)
(reg/v:SI 12 r12 [77])) 6 {*movsi} (insn_list 429 (nil))
(nil))
(insn 620 431 621 39 0x0 (set (reg:DI 2 r2)
(reg:DI 0 r0)) 7 {*movdi} (nil)
(nil))
(insn 621 620 432 39 0x0 (set (mem:DI (plus:SI (reg/f:SI 21 r21)
(const_int -8 [0xfffffff8])) [3 iw_u S8 A32])
(reg:DI 2 r2)) 7 {*movdi} (nil)
(nil))
(note 432 621 433 39 ("sqrt.c") 142)
(insn 433 432 436 39 0x1002f420 (set (reg:DF 14 r14 [70])
(reg:DF 0 r0)) 10 {*movdf} (insn_list 431 (nil))
(nil))
(note 436 433 443 39 ("sqrt.c") 145)
;; End of basic block 39, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(note 443 436 444 NOTE_INSN_FUNCTION_END)
(note 444 443 445 ("sqrt.c") 146)
;; Start of basic block 40, registers live: 20 [r20] 21 [r21] 30 [r30] 70
(code_label 445 444 520 40 1 "" [3 uses])
(note 520 445 446 40 [bb 40] NOTE_INSN_BASIC_BLOCK)
(insn 446 520 449 40 0x1002f480 (set (reg/i:DF 18 r18)
(reg:DF 14 r14 [70])) 10 {*movdf} (nil)
(nil))
(insn 449 446 586 40 0x1002f480 (use (reg/i:DF 18 r18)) -1 (insn_list 446 (nil))
(nil))
;; End of basic block 40, registers live:
18 [r18] 19 [r19] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
(note 586 449 0 NOTE_INSN_DELETED)
;; Function main
;; 0 regs to allocate:
;; 73 conflicts: 73 18 19 20 30
Spilling for insn 13.
Reloads for insn # 13
Reload 0: ADDR32_REGS, RELOAD_FOR_OPERAND_ADDRESS (opnum = 0), optional, can't combine, secondary_reload_p
Reload 1: reload_out (DF) = (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
NO_REGS, RELOAD_FOR_OUTPUT (opnum = 0), optional
reload_out_reg: (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
secondary_out_reload = 0
;; Register dispositions:
73 in 18
;; Hard regs used: 16 17 18 19 21 64
(note 1 0 3 ("sqrt.c") 151)
(note 3 1 7 NOTE_INSN_FUNCTION_BEG)
(note 7 3 27 ("sqrt.c") 152)
;; Start of basic block 0, registers live: 20 [r20] 21 [r21] 30 [r30]
(note 27 7 9 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(note 9 27 10 0 NOTE_INSN_DELETED)
(insn 10 9 11 0 0x0 (set (reg:DF 17 r17)
(mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])) 10 {*movdf} (insn_list 8 (nil))
(nil))
(call_insn 11 10 12 0 0x0 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__ieee754_sqrt")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 10 (nil))
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(nil))
(expr_list (use (reg:DF 17 r17))
(nil)))
(insn 12 11 13 0 0x0 (set (reg:DF 18 r18 [73])
(reg:DF 18 r18)) 10 {*movdf} (insn_list 11 (nil))
(expr_list:REG_EQUIV (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
(nil)))
(insn 13 12 14 0 0x0 (set (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
(reg:DF 18 r18 [73])) 10 {*movdf} (insn_list 12 (nil))
(nil))
(note 14 13 20 0 ("sqrt.c") 154)
(note 20 14 21 0 NOTE_INSN_FUNCTION_END)
(note 21 20 23 0 ("sqrt.c") 155)
(insn 23 21 26 0 0x0 (set (reg/i:SI 18 r18)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 26 23 30 0 0x0 (use (reg/i:SI 18 r18)) -1 (insn_list 23 (nil))
(nil))
;; End of basic block 0, registers live:
18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
(note 30 26 0 NOTE_INSN_DELETED)
[-- Attachment #3: 4049535085-sqrt.c.23.lreg --]
[-- Type: application/octet-stream, Size: 96100 bytes --]
;; Function __ieee754_sqrt
Pass 0
Register 70 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:732 MEM:1830
Register 71 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:416 ADDR32_REGS:416 DATA_REGS:0 GPR_REGS:416 ALL_REGS:1180 MEM:2950
Register 72 costs: ADDR8_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:0 DATA_REGS:110 GPR_REGS:110 ALL_REGS:280 MEM:700
Register 73 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:574 MEM:1435
Register 74 costs: LINK_REGS:5240 UADDR8_REGS:5240 SADDR8_REGS:5240 ADDR8_REGS:5240 UADDR16_REGS:5240 SADDR16_REGS:5240 ADDR16_REGS:5240 EVEN_REGS:7200 ADDR32_REGS:7200 DATA_REGS:5240 GPR_REGS:7200 ALL_REGS:22720 MEM:48940
Register 75 costs: LINK_REGS:3200 UADDR8_REGS:3200 SADDR8_REGS:3200 ADDR8_REGS:3200 UADDR16_REGS:3200 SADDR16_REGS:3200 ADDR16_REGS:3200 EVEN_REGS:5760 ADDR32_REGS:5760 DATA_REGS:3200 GPR_REGS:5760 ALL_REGS:8960 MEM:17600
Register 76 costs: LINK_REGS:2518 UADDR8_REGS:2518 SADDR8_REGS:2518 ADDR8_REGS:2518 UADDR16_REGS:2518 SADDR16_REGS:2518 ADDR16_REGS:2518 EVEN_REGS:2518 ADDR32_REGS:2518 DATA_REGS:2518 GPR_REGS:2518 ALL_REGS:5256 MEM:9363
Register 77 costs: LINK_REGS:4360 UADDR8_REGS:4360 SADDR8_REGS:4360 ADDR8_REGS:4360 UADDR16_REGS:4360 SADDR16_REGS:4360 ADDR16_REGS:4360 EVEN_REGS:4632 ADDR32_REGS:4632 DATA_REGS:4360 GPR_REGS:4632 ALL_REGS:22246 MEM:49075
Register 78 costs: LINK_REGS:60 UADDR8_REGS:60 SADDR8_REGS:60 ADDR8_REGS:60 UADDR16_REGS:60 SADDR16_REGS:60 ADDR16_REGS:60 EVEN_REGS:60 ADDR32_REGS:60 DATA_REGS:60 GPR_REGS:60 ALL_REGS:2710 MEM:6685
Register 79 costs: LINK_REGS:2236 UADDR8_REGS:2236 SADDR8_REGS:2236 ADDR8_REGS:2236 UADDR16_REGS:2236 SADDR16_REGS:2236 ADDR16_REGS:2236 EVEN_REGS:9126 ADDR32_REGS:9126 DATA_REGS:2236 GPR_REGS:9126 ALL_REGS:29824 MEM:71206
Register 80 costs: LINK_REGS:3000 UADDR8_REGS:3000 SADDR8_REGS:3000 ADDR8_REGS:3000 UADDR16_REGS:3000 SADDR16_REGS:3000 ADDR16_REGS:3000 EVEN_REGS:4280 ADDR32_REGS:4280 DATA_REGS:3000 GPR_REGS:4280 ALL_REGS:8056 MEM:15640
Register 81 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:3464 MEM:8330
Register 82 costs: LINK_REGS:440 UADDR8_REGS:440 SADDR8_REGS:440 ADDR8_REGS:440 UADDR16_REGS:440 SADDR16_REGS:440 ADDR16_REGS:440 EVEN_REGS:440 ADDR32_REGS:440 DATA_REGS:440 GPR_REGS:440 ALL_REGS:4140 MEM:9690
Register 83 costs: LINK_REGS:3640 UADDR8_REGS:3640 SADDR8_REGS:3640 ADDR8_REGS:3640 UADDR16_REGS:3640 SADDR16_REGS:3640 ADDR16_REGS:3640 EVEN_REGS:5600 ADDR32_REGS:5600 DATA_REGS:3640 GPR_REGS:5600 ALL_REGS:13800 MEM:29040
Register 84 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:110 GPR_REGS:220 ALL_REGS:1830 MEM:4410
Register 85 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:708 ADDR32_REGS:708 DATA_REGS:0 GPR_REGS:708 ALL_REGS:1062 MEM:2655
Register 86 costs: LINK_REGS:354 UADDR8_REGS:354 SADDR8_REGS:354 ADDR8_REGS:354 UADDR16_REGS:354 SADDR16_REGS:354 ADDR16_REGS:354 EVEN_REGS:354 ADDR32_REGS:354 DATA_REGS:354 GPR_REGS:354 ALL_REGS:1062 MEM:2124
Register 91 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:204 MEM:510
Register 97 costs: LINK_REGS:52 UADDR8_REGS:52 SADDR8_REGS:52 ADDR8_REGS:52 UADDR16_REGS:52 SADDR16_REGS:52 ADDR16_REGS:52 EVEN_REGS:52 ADDR32_REGS:52 DATA_REGS:52 GPR_REGS:52 ALL_REGS:260 MEM:572
Register 101 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:8 ADDR32_REGS:8 DATA_REGS:0 GPR_REGS:8 ALL_REGS:12 MEM:30
Register 104 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:8 MEM:20
Register 108 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:8 ADDR32_REGS:8 DATA_REGS:0 GPR_REGS:8 ALL_REGS:12 MEM:30
Register 113 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:1920 MEM:3840
Register 114 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:1920 MEM:3840
Register 115 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 116 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:440 MEM:770
Register 118 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 120 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:660 MEM:1320
Register 122 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 123 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 125 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:660 MEM:1320
Register 126 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:440 MEM:1100
Register 128 costs: LINK_REGS:2000 UADDR8_REGS:2000 SADDR8_REGS:2000 ADDR8_REGS:2000 UADDR16_REGS:2000 SADDR16_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:2000 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:6000 MEM:12000
Register 129 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:4000 MEM:10000
Register 131 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:1600 MEM:4000
Register 133 costs: LINK_REGS:960 UADDR8_REGS:960 SADDR8_REGS:960 ADDR8_REGS:960 UADDR16_REGS:960 SADDR16_REGS:960 ADDR16_REGS:960 EVEN_REGS:960 ADDR32_REGS:960 DATA_REGS:960 GPR_REGS:960 ALL_REGS:2880 MEM:5760
Register 134 costs: LINK_REGS:556 UADDR8_REGS:556 SADDR8_REGS:556 ADDR8_REGS:556 UADDR16_REGS:556 SADDR16_REGS:556 ADDR16_REGS:556 EVEN_REGS:556 ADDR32_REGS:556 DATA_REGS:556 GPR_REGS:556 ALL_REGS:1390 MEM:2641
Register 136 costs: LINK_REGS:1280 UADDR8_REGS:1280 SADDR8_REGS:1280 ADDR8_REGS:1280 UADDR16_REGS:1280 SADDR16_REGS:1280 ADDR16_REGS:1280 EVEN_REGS:1280 ADDR32_REGS:1280 DATA_REGS:1280 GPR_REGS:1280 ALL_REGS:3840 MEM:7680
Register 137 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:2560 MEM:6400
Register 143 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 148 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:120 MEM:300
Register 149 costs: LINK_REGS:12 UADDR8_REGS:12 SADDR8_REGS:12 ADDR8_REGS:12 UADDR16_REGS:12 SADDR16_REGS:12 ADDR16_REGS:12 EVEN_REGS:12 ADDR32_REGS:12 DATA_REGS:12 GPR_REGS:12 ALL_REGS:36 MEM:72
Register 153 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:1014 MEM:2535
Register 155 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 164 costs: LINK_REGS:1280 UADDR8_REGS:1280 SADDR8_REGS:1280 ADDR8_REGS:1280 UADDR16_REGS:1280 SADDR16_REGS:1280 ADDR16_REGS:1280 EVEN_REGS:1280 ADDR32_REGS:1280 DATA_REGS:1280 GPR_REGS:1280 ALL_REGS:3200 MEM:6080
Register 168 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:7040 MEM:16640
Register 170 costs: LINK_REGS:278 UADDR8_REGS:278 SADDR8_REGS:278 ADDR8_REGS:278 UADDR16_REGS:278 SADDR16_REGS:278 ADDR16_REGS:278 EVEN_REGS:278 ADDR32_REGS:278 DATA_REGS:278 GPR_REGS:278 ALL_REGS:2502 MEM:5838
Register 176 costs: LINK_REGS:96 UADDR8_REGS:96 SADDR8_REGS:96 ADDR8_REGS:96 UADDR16_REGS:96 SADDR16_REGS:96 ADDR16_REGS:96 EVEN_REGS:96 ADDR32_REGS:96 DATA_REGS:96 GPR_REGS:96 ALL_REGS:240 MEM:456
Register 177 costs: LINK_REGS:48 UADDR8_REGS:48 SADDR8_REGS:48 ADDR8_REGS:48 UADDR16_REGS:48 SADDR16_REGS:48 ADDR16_REGS:48 EVEN_REGS:48 ADDR32_REGS:48 DATA_REGS:48 GPR_REGS:48 ALL_REGS:432 MEM:1008
Register 70 pref GPR_REGS
Register 71 pref DATA_REGS
Register 72 pref ADDR32_REGS
Register 73 pref GPR_REGS
Register 74 pref DATA_REGS
Register 75 pref DATA_REGS
Register 76 pref GPR_REGS
Register 77 pref DATA_REGS
Register 78 pref GPR_REGS
Register 79 pref DATA_REGS
Register 80 pref DATA_REGS
Register 81 pref GPR_REGS
Register 82 pref GPR_REGS
Register 83 pref DATA_REGS
Register 84 pref DATA_REGS
Register 85 pref DATA_REGS
Register 86 pref GPR_REGS
Register 91 pref GPR_REGS
Register 97 pref GPR_REGS
Register 101 pref DATA_REGS
Register 104 pref GPR_REGS
Register 108 pref DATA_REGS
Register 113 pref GPR_REGS
Register 114 pref GPR_REGS
Register 115 pref GPR_REGS
Register 116 pref GPR_REGS
Register 118 pref GPR_REGS
Register 120 pref GPR_REGS
Register 122 pref GPR_REGS
Register 123 pref GPR_REGS
Register 125 pref GPR_REGS
Register 126 pref GPR_REGS
Register 128 pref GPR_REGS
Register 129 pref GPR_REGS
Register 131 pref GPR_REGS
Register 133 pref GPR_REGS
Register 134 pref GPR_REGS
Register 136 pref GPR_REGS
Register 137 pref GPR_REGS
Register 143 pref GPR_REGS
Register 148 pref GPR_REGS
Register 149 pref GPR_REGS
Register 153 pref GPR_REGS
Register 155 pref GPR_REGS
Register 164 pref GPR_REGS
Register 168 pref GPR_REGS
Register 170 pref GPR_REGS
Register 176 pref GPR_REGS
Register 177 pref GPR_REGS
Pass 1
Register 70 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:732 MEM:1830
Register 71 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:416 ADDR32_REGS:416 DATA_REGS:0 GPR_REGS:416 ALL_REGS:1180 MEM:2950
Register 72 costs: ADDR8_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:0 DATA_REGS:110 GPR_REGS:110 ALL_REGS:280 MEM:700
Register 73 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:574 MEM:1435
Register 74 costs: LINK_REGS:5240 UADDR8_REGS:5240 SADDR8_REGS:5240 ADDR8_REGS:5240 UADDR16_REGS:5240 SADDR16_REGS:5240 ADDR16_REGS:5240 EVEN_REGS:8480 ADDR32_REGS:8480 DATA_REGS:5240 GPR_REGS:8480 ALL_REGS:22720 MEM:48940
Register 75 costs: LINK_REGS:3200 UADDR8_REGS:3200 SADDR8_REGS:3200 ADDR8_REGS:3200 UADDR16_REGS:3200 SADDR16_REGS:3200 ADDR16_REGS:3200 EVEN_REGS:5760 ADDR32_REGS:5760 DATA_REGS:3200 GPR_REGS:5760 ALL_REGS:8960 MEM:17600
Register 76 costs: LINK_REGS:2518 UADDR8_REGS:2518 SADDR8_REGS:2518 ADDR8_REGS:2518 UADDR16_REGS:2518 SADDR16_REGS:2518 ADDR16_REGS:2518 EVEN_REGS:2518 ADDR32_REGS:2518 DATA_REGS:2518 GPR_REGS:2518 ALL_REGS:5256 MEM:9363
Register 77 costs: LINK_REGS:4360 UADDR8_REGS:4360 SADDR8_REGS:4360 ADDR8_REGS:4360 UADDR16_REGS:4360 SADDR16_REGS:4360 ADDR16_REGS:4360 EVEN_REGS:4632 ADDR32_REGS:4632 DATA_REGS:4360 GPR_REGS:4632 ALL_REGS:22246 MEM:49075
Register 78 costs: LINK_REGS:84 UADDR8_REGS:84 SADDR8_REGS:84 ADDR8_REGS:84 UADDR16_REGS:84 SADDR16_REGS:84 ADDR16_REGS:84 EVEN_REGS:84 ADDR32_REGS:84 DATA_REGS:84 GPR_REGS:84 ALL_REGS:2734 MEM:6709
Register 79 costs: LINK_REGS:2236 UADDR8_REGS:2236 SADDR8_REGS:2236 ADDR8_REGS:2236 UADDR16_REGS:2236 SADDR16_REGS:2236 ADDR16_REGS:2236 EVEN_REGS:13706 ADDR32_REGS:13706 DATA_REGS:2236 GPR_REGS:13706 ALL_REGS:29824 MEM:71206
Register 80 costs: LINK_REGS:3000 UADDR8_REGS:3000 SADDR8_REGS:3000 ADDR8_REGS:3000 UADDR16_REGS:3000 SADDR16_REGS:3000 ADDR16_REGS:3000 EVEN_REGS:4558 ADDR32_REGS:4558 DATA_REGS:3000 GPR_REGS:4558 ALL_REGS:8056 MEM:15640
Register 81 costs: LINK_REGS:316 UADDR8_REGS:316 SADDR8_REGS:316 ADDR8_REGS:316 UADDR16_REGS:316 SADDR16_REGS:316 ADDR16_REGS:316 EVEN_REGS:316 ADDR32_REGS:316 DATA_REGS:316 GPR_REGS:316 ALL_REGS:3560 MEM:8426
Register 82 costs: LINK_REGS:440 UADDR8_REGS:440 SADDR8_REGS:440 ADDR8_REGS:440 UADDR16_REGS:440 SADDR16_REGS:440 ADDR16_REGS:440 EVEN_REGS:440 ADDR32_REGS:440 DATA_REGS:440 GPR_REGS:440 ALL_REGS:4140 MEM:9690
Register 83 costs: LINK_REGS:3640 UADDR8_REGS:3640 SADDR8_REGS:3640 ADDR8_REGS:3640 UADDR16_REGS:3640 SADDR16_REGS:3640 ADDR16_REGS:3640 EVEN_REGS:5600 ADDR32_REGS:5600 DATA_REGS:3640 GPR_REGS:5600 ALL_REGS:13800 MEM:29040
Register 84 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:110 GPR_REGS:220 ALL_REGS:1830 MEM:4410
Register 85 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:708 ADDR32_REGS:708 DATA_REGS:0 GPR_REGS:708 ALL_REGS:1062 MEM:2655
Register 86 costs: LINK_REGS:354 UADDR8_REGS:354 SADDR8_REGS:354 ADDR8_REGS:354 UADDR16_REGS:354 SADDR16_REGS:354 ADDR16_REGS:354 EVEN_REGS:354 ADDR32_REGS:354 DATA_REGS:354 GPR_REGS:354 ALL_REGS:1062 MEM:2124
Register 91 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:204 MEM:510
Register 97 costs: LINK_REGS:52 UADDR8_REGS:52 SADDR8_REGS:52 ADDR8_REGS:52 UADDR16_REGS:52 SADDR16_REGS:52 ADDR16_REGS:52 EVEN_REGS:52 ADDR32_REGS:52 DATA_REGS:52 GPR_REGS:52 ALL_REGS:260 MEM:572
Register 101 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:8 ADDR32_REGS:8 DATA_REGS:0 GPR_REGS:8 ALL_REGS:12 MEM:30
Register 104 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:8 MEM:20
Register 108 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:8 ADDR32_REGS:8 DATA_REGS:0 GPR_REGS:8 ALL_REGS:12 MEM:30
Register 113 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:1920 MEM:3840
Register 114 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:1920 MEM:3840
Register 115 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 116 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:440 MEM:770
Register 118 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 120 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:660 MEM:1320
Register 122 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 123 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 125 costs: LINK_REGS:220 UADDR8_REGS:220 SADDR8_REGS:220 ADDR8_REGS:220 UADDR16_REGS:220 SADDR16_REGS:220 ADDR16_REGS:220 EVEN_REGS:220 ADDR32_REGS:220 DATA_REGS:220 GPR_REGS:220 ALL_REGS:660 MEM:1320
Register 126 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:440 MEM:1100
Register 128 costs: LINK_REGS:2000 UADDR8_REGS:2000 SADDR8_REGS:2000 ADDR8_REGS:2000 UADDR16_REGS:2000 SADDR16_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:2000 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:6000 MEM:12000
Register 129 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:4000 MEM:10000
Register 131 costs: LINK_REGS:640 UADDR8_REGS:640 SADDR8_REGS:640 ADDR8_REGS:640 UADDR16_REGS:640 SADDR16_REGS:640 ADDR16_REGS:640 EVEN_REGS:640 ADDR32_REGS:640 DATA_REGS:640 GPR_REGS:640 ALL_REGS:2240 MEM:4640
Register 133 costs: LINK_REGS:960 UADDR8_REGS:960 SADDR8_REGS:960 ADDR8_REGS:960 UADDR16_REGS:960 SADDR16_REGS:960 ADDR16_REGS:960 EVEN_REGS:960 ADDR32_REGS:960 DATA_REGS:960 GPR_REGS:960 ALL_REGS:2880 MEM:5760
Register 134 costs: LINK_REGS:834 UADDR8_REGS:834 SADDR8_REGS:834 ADDR8_REGS:834 UADDR16_REGS:834 SADDR16_REGS:834 ADDR16_REGS:834 EVEN_REGS:834 ADDR32_REGS:834 DATA_REGS:834 GPR_REGS:834 ALL_REGS:1668 MEM:2919
Register 136 costs: LINK_REGS:1280 UADDR8_REGS:1280 SADDR8_REGS:1280 ADDR8_REGS:1280 UADDR16_REGS:1280 SADDR16_REGS:1280 ADDR16_REGS:1280 EVEN_REGS:1280 ADDR32_REGS:1280 DATA_REGS:1280 GPR_REGS:1280 ALL_REGS:3840 MEM:7680
Register 137 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:2560 MEM:6400
Register 143 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:220 MEM:550
Register 148 costs: LINK_REGS:0 UADDR8_REGS:0 SADDR8_REGS:0 ADDR8_REGS:0 UADDR16_REGS:0 SADDR16_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:120 MEM:300
Register 149 costs: LINK_REGS:24 UADDR8_REGS:24 SADDR8_REGS:24 ADDR8_REGS:24 UADDR16_REGS:24 SADDR16_REGS:24 ADDR16_REGS:24 EVEN_REGS:24 ADDR32_REGS:24 DATA_REGS:24 GPR_REGS:24 ALL_REGS:48 MEM:84
Register 153 costs: ADDR8_REGS:0 ADDR16_REGS:0 EVEN_REGS:0 ADDR32_REGS:0 DATA_REGS:0 GPR_REGS:0 ALL_REGS:1014 MEM:2535
Register 155 costs: LINK_REGS:110 UADDR8_REGS:110 SADDR8_REGS:110 ADDR8_REGS:110 UADDR16_REGS:110 SADDR16_REGS:110 ADDR16_REGS:110 EVEN_REGS:110 ADDR32_REGS:110 DATA_REGS:110 GPR_REGS:110 ALL_REGS:330 MEM:660
Register 164 costs: LINK_REGS:1920 UADDR8_REGS:1920 SADDR8_REGS:1920 ADDR8_REGS:1920 UADDR16_REGS:1920 SADDR16_REGS:1920 ADDR16_REGS:1920 EVEN_REGS:1920 ADDR32_REGS:1920 DATA_REGS:1920 GPR_REGS:1920 ALL_REGS:3840 MEM:6720
Register 168 costs: LINK_REGS:3200 UADDR8_REGS:3200 SADDR8_REGS:3200 ADDR8_REGS:3200 UADDR16_REGS:3200 SADDR16_REGS:3200 ADDR16_REGS:3200 EVEN_REGS:3200 ADDR32_REGS:3200 DATA_REGS:3200 GPR_REGS:3200 ALL_REGS:9600 MEM:19200
Register 170 costs: LINK_REGS:834 UADDR8_REGS:834 SADDR8_REGS:834 ADDR8_REGS:834 UADDR16_REGS:834 SADDR16_REGS:834 ADDR16_REGS:834 EVEN_REGS:834 ADDR32_REGS:834 DATA_REGS:834 GPR_REGS:834 ALL_REGS:3058 MEM:6394
Register 176 costs: LINK_REGS:144 UADDR8_REGS:144 SADDR8_REGS:144 ADDR8_REGS:144 UADDR16_REGS:144 SADDR16_REGS:144 ADDR16_REGS:144 EVEN_REGS:144 ADDR32_REGS:144 DATA_REGS:144 GPR_REGS:144 ALL_REGS:288 MEM:504
Register 177 costs: LINK_REGS:192 UADDR8_REGS:192 SADDR8_REGS:192 ADDR8_REGS:192 UADDR16_REGS:192 SADDR16_REGS:192 ADDR16_REGS:192 EVEN_REGS:192 ADDR32_REGS:192 DATA_REGS:192 GPR_REGS:192 ALL_REGS:576 MEM:1152
182 registers.
Register 70 used 5 times across 9 insns; set 4 times; 8 bytes.
Register 71 used 10 times across 30 insns; set 1 time; user var; dies in 2 places; crosses 2 calls; 8 bytes; pref DATA_REGS.
Register 72 used 3 times across 22 insns; set 1 time; user var; crosses 1 call; 8 bytes; pref ADDR32_REGS.
Register 73 used 2 times across 2 insns in block 19; set 1 time; user var.
Register 74 used 14 times across 116 insns; set 4 times; user var; dies in 0 places; pref DATA_REGS.
Register 75 used 6 times across 31 insns; set 1 time; user var; pref DATA_REGS.
Register 76 used 4 times across 120 insns; set 2 times; user var; dies in 0 places.
Register 77 used 29 times across 131 insns; set 10 times; user var; dies in 2 places; pref DATA_REGS.
Register 78 used 12 times across 194 insns; set 5 times; user var; crosses 2 calls.
Register 79 used 48 times across 140 insns; set 16 times; user var; dies in 2 places; pref DATA_REGS.
Register 80 used 6 times across 120 insns; set 3 times; user var; dies in 0 places; pref DATA_REGS.
Register 81 used 11 times across 198 insns; set 5 times; user var; crosses 2 calls.
Register 82 used 14 times across 147 insns; set 6 times; user var; dies in 2 places; crosses 2 calls.
Register 83 used 8 times across 31 insns; set 2 times; user var; dies in 2 places; pref DATA_REGS.
Register 84 used 6 times across 32 insns; set 2 times; user var; pref DATA_REGS.
Register 85 used 3 times across 3 insns in block 0; set 1 time; user var; 8 bytes; pref DATA_REGS.
Register 86 used 2 times across 2 insns in block 0; set 1 time.
Register 91 used 2 times across 2 insns in block 1; set 1 time; 8 bytes.
Register 97 used 4 times across 5 insns in block 3; set 2 times.
Register 101 used 3 times across 18 insns in block 6; set 1 time; crosses 1 call; pref DATA_REGS; pointer.
Register 104 used 2 times across 7 insns in block 6; set 1 time; crosses 1 call; 8 bytes.
Register 108 used 3 times across 4 insns in block 6; set 1 time; 8 bytes; pref DATA_REGS.
Register 113 used 2 times across 2 insns in block 9; set 1 time.
Register 114 used 2 times across 2 insns in block 11; set 1 time.
Register 115 used 2 times across 2 insns in block 12; set 1 time.
Register 116 used 2 times across 2 insns in block 12; set 1 time.
Register 118 used 2 times across 2 insns in block 12; set 1 time.
Register 120 used 2 times across 2 insns in block 13; set 1 time.
Register 122 used 2 times across 2 insns in block 14; set 1 time.
Register 123 used 2 times across 2 insns in block 14; set 1 time.
Register 125 used 2 times across 2 insns in block 15; set 1 time.
Register 126 used 2 times across 2 insns in block 15; set 1 time.
Register 128 used 2 times across 2 insns in block 18; set 1 time.
Register 129 used 2 times across 2 insns in block 18; set 1 time.
Register 131 used 3 times across 10 insns; set 2 times.
Register 133 used 2 times across 2 insns in block 24; set 1 time.
Register 134 used 3 times across 3 insns in block 25; set 1 time.
Register 136 used 2 times across 2 insns in block 29; set 1 time.
Register 137 used 2 times across 2 insns in block 29; set 1 time.
Register 143 used 2 times across 2 insns in block 31; set 1 time.
Register 148 used 2 times across 2 insns in block 34; set 1 time.
Register 149 used 2 times across 2 insns in block 36; set 1 time.
Register 153 used 6 times across 330 insns; set 3 times; user var; crosses 2 calls; 8 bytes.
Register 155 used 2 times across 2 insns in block 10; set 1 time.
Register 164 used 3 times across 3 insns in block 21; set 1 time.
Register 168 used 10 times across 14 insns; set 5 times.
Register 170 used 8 times across 8 insns in block 25; set 4 times.
Register 176 used 3 times across 3 insns in block 35; set 1 time.
Register 177 used 8 times across 8 insns in block 35; set 4 times.
40 basic blocks, 65 edges.
Basic block 0: first insn 450, last 28, prev -1, next 1, loop_depth 0, count 0, freq 1775, maybe hot.
Predecessors: ENTRY [100.0%] (fallthru)
Successors: 1 [29.0%] (fallthru) 2 [71.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
Registers live at end: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Basic block 1: first insn 452, last 51, prev 0, next 2, loop_depth 0, count 0, freq 515, maybe hot.
Predecessors: 0 [29.0%] (fallthru)
Successors: 40 [100.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
Basic block 2: first insn 53, last 56, prev 1, next 3, loop_depth 0, count 0, freq 1260, maybe hot.
Predecessors: 0 [71.0%]
Successors: 3 [21.0%] (fallthru) 7 [79.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Registers live at end: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Basic block 3: first insn 454, last 64, prev 2, next 5, loop_depth 0, count 0, freq 265, maybe hot.
Predecessors: 2 [21.0%] (fallthru)
Successors: 5 [50.0%] (fallthru) 40 [50.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Registers live at end: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 71 77 79 153
Basic block 5: first insn 457, last 76, prev 3, next 6, loop_depth 0, count 0, freq 132, maybe hot.
Predecessors: 3 [50.0%] (fallthru)
Successors: 6 [21.0%] (fallthru) 7 [79.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Registers live at end: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
Basic block 6: first insn 458, last 105, prev 5, next 7, loop_depth 0, count 0, freq 28, maybe hot.
Predecessors: 5 [21.0%] (fallthru)
Successors: 40 [100.0%]
Registers live at start: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
Basic block 7: first insn 109, last 114, prev 6, next 8, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 5 [79.0%] 2 [79.0%]
Successors: 8 [50.0%] (fallthru) 13 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 8: first insn 550, last 522, prev 7, next 9, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 7 [50.0%] (fallthru)
Successors: 9 [64.0%] (fallthru) 10 [36.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 9: first insn 136, last 121, prev 8, next 10, loop_depth 1, count 0, freq 3200, maybe hot.
Predecessors: 9 [89.0%] (dfs_back) 8 [64.0%] (fallthru)
Successors: 10 [11.0%] (fallthru,9) 9 [89.0%] (dfs_back)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 10: first insn 523, last 530, prev 9, next 11, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 9 [11.0%] (fallthru,9) 8 [36.0%]
Successors: 11 [64.0%] (fallthru) 12 [36.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
Basic block 11: first insn 160, last 149, prev 10, next 12, loop_depth 1, count 0, freq 3200, maybe hot.
Predecessors: 11 [89.0%] (dfs_back) 10 [64.0%] (fallthru)
Successors: 12 [11.0%] (fallthru,9) 11 [89.0%] (dfs_back)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
Basic block 12: first insn 531, last 176, prev 11, next 13, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 11 [11.0%] (fallthru,9) 10 [36.0%]
Successors: 13 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 13: first insn 177, last 186, prev 12, next 14, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 12 [100.0%] (fallthru) 7 [50.0%]
Successors: 14 [50.0%] (fallthru) 15 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 14: first insn 475, last 195, prev 13, next 15, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 13 [50.0%] (fallthru)
Successors: 15 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 15: first insn 196, last 212, prev 14, next 16, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 14 [100.0%] (fallthru) 13 [50.0%]
Successors: 16 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 16: first insn 248, last 228, prev 15, next 17, loop_depth 1, count 0, freq 10000, maybe hot.
Predecessors: 18 [89.0%] (dfs_back) 15 [100.0%] (fallthru)
Successors: 17 [50.0%] (fallthru) 18 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 83 153
Basic block 17: first insn 478, last 236, prev 16, next 18, loop_depth 1, count 0, freq 5000, maybe hot.
Predecessors: 16 [50.0%] (fallthru)
Successors: 18 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 81 82 83 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 18: first insn 237, last 217, prev 17, next 19, loop_depth 1, count 0, freq 10000, maybe hot.
Predecessors: 17 [100.0%] (fallthru) 16 [50.0%]
Successors: 19 [11.0%] (fallthru,9) 16 [89.0%] (dfs_back)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 19: first insn 483, last 544, prev 18, next 20, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 18 [11.0%] (fallthru,9)
Successors: 20 [64.0%] (fallthru) 30 [36.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 20: first insn 328, last 274, prev 19, next 21, loop_depth 1, count 0, freq 6400, maybe hot.
Predecessors: 29 [89.0%] (dfs_back) 19 [64.0%] (fallthru)
Successors: 21 [50.0%] (fallthru) 24 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Basic block 21: first insn 485, last 282, prev 20, next 22, loop_depth 1, count 0, freq 3200, maybe hot.
Predecessors: 20 [50.0%] (fallthru)
Successors: 22 [50.0%] (fallthru) 23 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
Basic block 22: first insn 488, last 283, prev 21, next 23, loop_depth 1, count 0, freq 1600, maybe hot.
Predecessors: 21 [50.0%] (fallthru)
Successors: 23 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 168
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
Basic block 23: first insn 284, last 287, prev 22, next 24, loop_depth 1, count 0, freq 3200, maybe hot.
Predecessors: 22 [100.0%] (fallthru) 21 [50.0%]
Successors: 24 [50.0%] (fallthru) 29 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Basic block 24: first insn 290, last 298, prev 23, next 25, loop_depth 1, count 0, freq 4800, maybe hot.
Predecessors: 23 [50.0%] (fallthru) 20 [50.0%]
Successors: 25 [29.0%] (fallthru) 26 [71.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 77 78 79 80 81 82 83 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Basic block 25: first insn 492, last 573, prev 24, next 26, loop_depth 1, count 0, freq 1392, maybe hot.
Predecessors: 24 [29.0%] (fallthru)
Successors: 26 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Basic block 26: first insn 304, last 309, prev 25, next 27, loop_depth 1, count 0, freq 4800, maybe hot.
Predecessors: 25 [100.0%] (fallthru) 24 [71.0%]
Successors: 27 [50.0%] (fallthru) 28 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
Basic block 27: first insn 495, last 311, prev 26, next 28, loop_depth 1, count 0, freq 2400, maybe hot.
Predecessors: 26 [50.0%] (fallthru)
Successors: 28 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
Basic block 28: first insn 312, last 316, prev 27, next 29, loop_depth 1, count 0, freq 4800, maybe hot.
Predecessors: 27 [100.0%] (fallthru) 26 [50.0%]
Successors: 29 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 29: first insn 317, last 261, prev 28, next 30, loop_depth 1, count 0, freq 6400, maybe hot.
Predecessors: 28 [100.0%] (fallthru) 23 [50.0%]
Successors: 30 [11.0%] (fallthru,9) 20 [89.0%] (dfs_back)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
Basic block 30: first insn 545, last 338, prev 29, next 31, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 29 [11.0%] (fallthru,9) 19 [36.0%]
Successors: 31 [50.0%] (fallthru) 37 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 78 79 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Basic block 31: first insn 502, last 354, prev 30, next 32, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 30 [50.0%] (fallthru)
Successors: 32 [79.0%] (fallthru) 37 [21.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
Basic block 32: first insn 504, last 364, prev 31, next 33, loop_depth 0, count 0, freq 434, maybe hot.
Predecessors: 31 [79.0%] (fallthru)
Successors: 33 [29.0%] (fallthru) 34 [71.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
Basic block 33: first insn 505, last 371, prev 32, next 34, loop_depth 0, count 0, freq 126, maybe hot.
Predecessors: 32 [29.0%] (fallthru)
Successors: 37 [100.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Basic block 34: first insn 373, last 385, prev 33, next 35, loop_depth 0, count 0, freq 308, maybe hot.
Predecessors: 32 [71.0%]
Successors: 35 [79.0%] (fallthru) 36 [21.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Basic block 35: first insn 508, last 399, prev 34, next 36, loop_depth 0, count 0, freq 244, maybe hot.
Predecessors: 34 [79.0%] (fallthru)
Successors: 37 [100.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Basic block 36: first insn 401, last 404, prev 35, next 37, loop_depth 0, count 0, freq 65, maybe hot.
Predecessors: 34 [21.0%]
Successors: 37 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Basic block 37: first insn 408, last 417, prev 36, next 38, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 36 [100.0%] (fallthru) 35 [100.0%] 33 [100.0%] 31 [21.0%] 30 [50.0%]
Successors: 38 [50.0%] (fallthru) 39 [50.0%]
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 38: first insn 516, last 419, prev 37, next 39, loop_depth 0, count 0, freq 550, maybe hot.
Predecessors: 37 [50.0%] (fallthru)
Successors: 39 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Basic block 39: first insn 420, last 436, prev 38, next 40, loop_depth 0, count 0, freq 1100, maybe hot.
Predecessors: 38 [100.0%] (fallthru) 37 [50.0%]
Successors: 40 [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
Registers live at end: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
Basic block 40: first insn 445, last 449, prev 39, next -2, loop_depth 0, count 0, freq 1775, maybe hot.
Predecessors: 3 [50.0%] 39 [100.0%] (fallthru) 6 [100.0%] 1 [100.0%]
Successors: EXIT [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
Registers live at end: 18 [r18] 19 [r19] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
;; Register 73 in 0.
;; Register 85 in 0.
;; Register 86 in 0.
;; Register 91 in 18.
;; Register 97 in 0.
;; Register 101 in 6.
;; Register 104 in 4.
;; Register 108 in 0.
;; Register 113 in 0.
;; Register 114 in 0.
;; Register 115 in 0.
;; Register 116 in 0.
;; Register 118 in 0.
;; Register 120 in 0.
;; Register 122 in 0.
;; Register 123 in 0.
;; Register 125 in 0.
;; Register 126 in 0.
;; Register 128 in 0.
;; Register 129 in 0.
;; Register 133 in 0.
;; Register 134 in 1.
;; Register 136 in 0.
;; Register 137 in 0.
;; Register 143 in 18.
;; Register 148 in 18.
;; Register 149 in 0.
;; Register 155 in 0.
;; Register 164 in 0.
;; Register 170 in 0.
;; Register 176 in 1.
;; Register 177 in 0.
(note 1 0 450 ("sqrt.c") 15)
;; Start of basic block 0, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
(note 450 1 581 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(insn 581 450 3 0 0x0 (set (reg/v:DI 153)
(const_int 0 [0x0])) 7 {*movdi} (nil)
(nil))
(insn 3 581 4 0 0x0 (set (reg/v:DF 71)
(reg:DF 17 r17)) 10 {*movdf} (nil)
(nil))
(note 4 3 8 0 NOTE_INSN_FUNCTION_BEG)
(note 8 4 9 0 ("sqrt.c") 16)
(note 9 8 11 0 ("sqrt.c") 17)
(note 11 9 12 0 ("sqrt.c") 18)
(note 12 11 16 0 ("sqrt.c") 19)
(note 16 12 17 0 ("sqrt.c") 23)
(note 17 16 18 0 ("sqrt.c") 24)
(insn 18 17 19 0 0x1002f390 (set (subreg:DF (reg/v:DI 85) 0)
(reg/v:DF 71)) 10 {*movdf} (insn_list 3 (nil))
(nil))
(note 19 18 20 0 ("sqrt.c") 25)
(insn 20 19 21 0 0x1002f390 (set (reg/v:SI 79)
(subreg:SI (reg/v:DI 85) 4)) 6 {*movsi} (insn_list 18 (nil))
(nil))
(note 21 20 22 0 ("sqrt.c") 26)
(insn 22 21 25 0 0x1002f390 (set (reg/v:SI 77)
(subreg:SI (reg/v:DI 85) 0)) 6 {*movsi} (nil)
(expr_list:REG_DEAD (reg/v:DI 85)
(nil)))
(note 25 22 26 0 ("sqrt.c") 31)
(insn 26 25 27 0 0x1002f450 (set (reg:SI 86)
(and:SI (reg/v:SI 79)
(const_int 2146435072 [0x7ff00000]))) 25 {andsi3} (insn_list 20 (nil))
(nil))
(insn:QI 27 26 28 0 0x1002f450 (set (cc0)
(compare:SI (reg:SI 86)
(const_int 2146435072 [0x7ff00000]))) 29 {cmpsi_internal} (insn_list 26 (nil))
(expr_list:REG_DEAD (reg:SI 86)
(nil)))
(jump_insn 28 27 31 0 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 53)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 0, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 31 28 452 ("sqrt.c") 33)
;; Start of basic block 1, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71
(note 452 31 34 1 [bb 1] NOTE_INSN_BASIC_BLOCK)
(note 34 452 38 1 NOTE_INSN_DELETED)
(insn 38 34 39 1 0x1002f450 (set (reg:SI 19 r19)
(subreg:SI (reg/v:DF 71) 0)) 6 {*movsi} (nil)
(insn_list:REG_LIBCALL 41 (nil)))
(insn 39 38 40 1 0x1002f450 (set (reg:SI 0 r0)
(subreg:SI (reg/v:DF 71) 4)) 6 {*movsi} (nil)
(nil))
(call_insn/u 40 39 41 1 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__muldf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 39 (insn_list 38 (nil)))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil)))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 41 40 42 1 0x1002f450 (set (reg:DF 91)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 40 (nil))
(expr_list:REG_DEAD (reg:DF 18 r18)
(insn_list:REG_RETVAL 38 (expr_list:REG_EQUAL (mult:DF (reg:DF 17 r17)
(reg:DF 17 r17))
(nil)))))
(note 42 41 43 1 NOTE_INSN_DELETED)
(insn 43 42 46 1 0x1002f450 (set (reg:DF 17 r17)
(reg:DF 91)) 10 {*movdf} (insn_list 41 (nil))
(expr_list:REG_DEAD (reg:DF 91)
(insn_list:REG_LIBCALL 49 (nil))))
(insn 46 43 47 1 0x1002f450 (set (reg:SI 19 r19)
(subreg:SI (reg/v:DF 71) 0)) 6 {*movsi} (nil)
(nil))
(insn 47 46 48 1 0x1002f450 (set (reg:SI 0 r0)
(subreg:SI (reg/v:DF 71) 4)) 6 {*movsi} (nil)
(expr_list:REG_DEAD (reg/v:DF 71)
(nil)))
(call_insn/u 48 47 49 1 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__adddf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 47 (insn_list 46 (insn_list 43 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil)))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 49 48 51 1 0x1002f450 (set (reg:DF 70)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 48 (nil))
(expr_list:REG_DEAD (reg:DF 18 r18)
(insn_list:REG_RETVAL 43 (expr_list:REG_EQUAL (plus:DF (reg:DF 91)
(reg/v:DF 71))
(nil)))))
(jump_insn 51 49 52 1 0x1002f450 (set (pc)
(label_ref 445)) 35 {jump} (nil)
(nil))
;; End of basic block 1, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(barrier 52 51 53)
;; Start of basic block 2, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(code_label 53 52 453 2 3 "" [1 uses])
(note 453 53 54 2 [bb 2] NOTE_INSN_BASIC_BLOCK)
(note 54 453 55 2 ("sqrt.c") 37)
(insn:QI 55 54 56 2 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 79)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 56 55 59 2 0x1002f450 (set (pc)
(if_then_else (gt (cc0)
(const_int 0 [0x0]))
(label_ref 109)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7900 [0x1edc])
(nil)))
;; End of basic block 2, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 59 56 454 ("sqrt.c") 39)
;; Start of basic block 3, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 454 59 61 3 [bb 3] NOTE_INSN_BASIC_BLOCK)
(insn 61 454 62 3 0x1002f450 (set (reg:SI 97)
(and:SI (reg/v:SI 79)
(const_int 2147483647 [0x7fffffff]))) 25 {andsi3} (nil)
(nil))
(insn 62 61 68 3 0x1002f450 (set (reg:SI 97)
(ior:SI (reg:SI 97)
(reg/v:SI 77))) 26 {iorsi3} (insn_list 61 (nil))
(nil))
(insn 68 62 63 3 0x1002f450 (set (reg:DF 70)
(reg/v:DF 71)) 10 {*movdf} (nil)
(nil))
(insn:QI 63 68 64 3 0x1002f450 (set (cc0)
(compare:SI (reg:SI 97)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 62 (nil))
(expr_list:REG_DEAD (reg:SI 97)
(nil)))
(jump_insn 64 63 65 3 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 445)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 3, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70 71 77 79 153
(note 65 64 457 ("sqrt.c") 40)
;; Start of basic block 5, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 457 65 74 5 [bb 5] NOTE_INSN_BASIC_BLOCK)
(note 74 457 75 5 ("sqrt.c") 41)
(insn:QI 75 74 76 5 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 79)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 76 75 77 5 0x1002f450 (set (pc)
(if_then_else (ge (cc0)
(const_int 0 [0x0]))
(label_ref 109)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7900 [0x1edc])
(nil)))
;; End of basic block 5, registers live:
17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71 77 79 153
(note 77 76 458 ("sqrt.c") 42)
;; Start of basic block 6, registers live: 17 [r17] 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap] 71
(note 458 77 80 6 [bb 6] NOTE_INSN_BASIC_BLOCK)
(insn 80 458 84 6 0x1002f450 (set (reg/f:SI 101)
(symbol_ref:SI ("__subdf3"))) 6 {*movsi} (nil)
(expr_list:REG_EQUIV (symbol_ref:SI ("__subdf3"))
(nil)))
(insn 84 80 85 6 0x1002f450 (set (reg:SI 19 r19)
(subreg:SI (reg/v:DF 71) 0)) 6 {*movsi} (nil)
(insn_list:REG_LIBCALL 87 (nil)))
(insn 85 84 86 6 0x1002f450 (set (reg:SI 0 r0)
(subreg:SI (reg/v:DF 71) 4)) 6 {*movsi} (nil)
(nil))
(call_insn/u 86 85 87 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (reg/f:SI 101) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 80 (insn_list 84 (insn_list 85 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil)))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 87 86 89 6 0x1002f450 (set (reg:DF 104)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 86 (nil))
(expr_list:REG_DEAD (reg:DF 18 r18)
(insn_list:REG_RETVAL 84 (expr_list:REG_EQUAL (minus:DF (reg:DF 17 r17)
(reg:DF 17 r17))
(nil)))))
(insn 89 87 92 6 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 71)) 10 {*movdf} (nil)
(expr_list:REG_DEAD (reg/v:DF 71)
(insn_list:REG_LIBCALL 95 (nil))))
(insn 92 89 93 6 0x1002f450 (set (reg:SI 19 r19)
(reg:SI 17 r17)) 6 {*movsi} (nil)
(nil))
(insn 93 92 94 6 0x1002f450 (set (reg:SI 0 r0)
(reg:SI 18 r18)) 6 {*movsi} (nil)
(nil))
(call_insn/u 94 93 95 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (reg/f:SI 101) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 89 (insn_list 92 (insn_list 93 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_DEAD (reg/f:SI 101)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 95 94 96 6 0x1002f450 (set (reg:DF 108)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 94 (nil))
(expr_list:REG_DEAD (reg:DF 18 r18)
(insn_list:REG_RETVAL 89 (expr_list:REG_EQUAL (minus:DF (reg/v:DF 71)
(reg/v:DF 71))
(nil)))))
(note 96 95 97 6 NOTE_INSN_DELETED)
(insn 97 96 100 6 0x1002f450 (set (reg:DF 17 r17)
(reg:DF 104)) 10 {*movdf} (insn_list 87 (nil))
(expr_list:REG_DEAD (reg:DF 104)
(insn_list:REG_LIBCALL 103 (nil))))
(insn 100 97 101 6 0x1002f450 (set (reg:SI 19 r19)
(subreg:SI (reg:DF 108) 0)) 6 {*movsi} (insn_list 95 (nil))
(nil))
(insn 101 100 102 6 0x1002f450 (set (reg:SI 0 r0)
(subreg:SI (reg:DF 108) 4)) 6 {*movsi} (nil)
(expr_list:REG_DEAD (reg:DF 108)
(nil)))
(call_insn/u 102 101 103 6 0x1002f450 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__divdf3")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 101 (insn_list 100 (insn_list 97 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil)))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 103 102 105 6 0x1002f450 (set (reg:DF 70)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 102 (nil))
(expr_list:REG_DEAD (reg:DF 18 r18)
(insn_list:REG_RETVAL 97 (expr_list:REG_EQUAL (div:DF (reg:DF 104)
(reg:DF 108))
(nil)))))
(jump_insn 105 103 106 6 0x1002f450 (set (pc)
(label_ref 445)) 35 {jump} (nil)
(nil))
;; End of basic block 6, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(barrier 106 105 109)
;; Start of basic block 7, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 153
(code_label 109 106 461 7 4 "" [2 uses])
(note 461 109 110 7 [bb 7] NOTE_INSN_BASIC_BLOCK)
(note 110 461 111 7 ("sqrt.c") 45)
(insn 111 110 112 7 0x1002f450 (set (reg/v:SI 82)
(ashiftrt:SI (reg/v:SI 79)
(const_int 20 [0x14]))) 23 {ashrsi3} (nil)
(nil))
(note 112 111 113 7 ("sqrt.c") 46)
(insn:QI 113 112 114 7 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 82)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 111 (nil))
(nil))
(jump_insn 114 113 117 7 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 177)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 7, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 117 114 550 ("sqrt.c") 48)
;; Start of basic block 8, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 550 117 521 8 [bb 8] NOTE_INSN_BASIC_BLOCK)
(insn:QI 521 550 522 8 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 79)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 522 521 118 8 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 523)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 8, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 118 522 136 NOTE_INSN_LOOP_BEG)
;; Start of basic block 9, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(code_label 136 118 463 9 12 "" [1 uses])
(note 463 136 128 9 [bb 9] NOTE_INSN_BASIC_BLOCK)
(note 128 463 129 9 ("sqrt.c") 50)
(insn 129 128 130 9 0x1002f450 (set (reg/v:SI 82)
(plus:SI (reg/v:SI 82)
(const_int -21 [0xffffffeb]))) 12 {addsi3} (nil)
(nil))
(note 130 129 131 9 ("sqrt.c") 51)
(insn 131 130 132 9 0x1002f450 (set (reg:SI 113)
(lshiftrt:SI (reg/v:SI 77)
(const_int 11 [0xb]))) 24 {lshrsi3} (nil)
(nil))
(insn 132 131 133 9 0x1002f450 (set (reg/v:SI 79)
(ior:SI (reg/v:SI 79)
(reg:SI 113))) 26 {iorsi3} (insn_list 131 (nil))
(expr_list:REG_DEAD (reg:SI 113)
(nil)))
(note 133 132 134 9 ("sqrt.c") 52)
(insn 134 133 135 9 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(const_int 21 [0x15]))) 22 {ashlsi3} (nil)
(nil))
(note 135 134 527 9 NOTE_INSN_LOOP_CONT)
(note 527 135 120 9 NOTE_INSN_LOOP_VTOP)
(insn:QI 120 527 121 9 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 79)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 132 (nil))
(nil))
(jump_insn 121 120 141 9 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 136)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 9, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 141 121 523 NOTE_INSN_LOOP_END)
;; Start of basic block 10, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(code_label 523 141 467 10 46 "" [1 uses])
(note 467 523 143 10 [bb 10] NOTE_INSN_BASIC_BLOCK)
(note 143 467 144 10 ("sqrt.c") 54)
(insn 144 143 528 10 0x1002f450 (set (reg/v:SI 84)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 528 144 529 10 0x1002f450 (set (reg:SI 155)
(and:SI (reg/v:SI 79)
(const_int 1048576 [0x100000]))) 25 {andsi3} (nil)
(nil))
(insn:QI 529 528 530 10 0x1002f450 (set (cc0)
(compare:SI (reg:SI 155)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 528 (nil))
(expr_list:REG_DEAD (reg:SI 155)
(nil)))
(jump_insn 530 529 145 10 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 531)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 10, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(note 145 530 160 NOTE_INSN_LOOP_BEG)
;; Start of basic block 11, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(code_label 160 145 468 11 17 "" [1 uses])
(note 468 160 154 11 [bb 11] NOTE_INSN_BASIC_BLOCK)
(note 154 468 155 11 ("sqrt.c") 55)
(insn 155 154 156 11 0x1002f450 (set (reg/v:SI 79)
(ashift:SI (reg/v:SI 79)
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 156 155 157 11 ("sqrt.c") 54)
(note 157 156 159 11 NOTE_INSN_LOOP_CONT)
(insn 159 157 535 11 0x1002f450 (set (reg/v:SI 84)
(plus:SI (reg/v:SI 84)
(const_int 1 [0x1]))) 12 {addsi3} (nil)
(nil))
(note 535 159 147 11 NOTE_INSN_LOOP_VTOP)
(insn 147 535 148 11 0x1002f450 (set (reg/s:SI 114)
(and:SI (reg/v:SI 79)
(const_int 1048576 [0x100000]))) 25 {andsi3} (insn_list 155 (nil))
(nil))
(insn:QI 148 147 149 11 0x1002f450 (set (cc0)
(compare:SI (reg/s:SI 114)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 147 (nil))
(expr_list:REG_DEAD (reg/s:SI 114)
(nil)))
(jump_insn 149 148 165 11 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 160)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 11, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(note 165 149 531 NOTE_INSN_LOOP_END)
;; Start of basic block 12, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 84 153
(code_label 531 165 473 12 48 "" [1 uses])
(note 473 531 167 12 [bb 12] NOTE_INSN_BASIC_BLOCK)
(note 167 473 168 12 ("sqrt.c") 56)
(insn 168 167 169 12 0x1002f450 (set (reg:SI 115)
(minus:SI (reg/v:SI 82)
(reg/v:SI 84))) 13 {subsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 82)
(nil)))
(insn 169 168 170 12 0x1002f450 (set (reg/v:SI 82)
(plus:SI (reg:SI 115)
(const_int 1 [0x1]))) 12 {addsi3} (insn_list 168 (nil))
(expr_list:REG_DEAD (reg:SI 115)
(nil)))
(note 170 169 171 12 ("sqrt.c") 57)
(note 171 170 172 12 NOTE_INSN_DELETED)
(insn 172 171 173 12 0x1002f450 (set (reg:SI 116)
(neg:SI (reg/v:SI 84))) 15 {negsi2} (nil)
(nil))
(insn 173 172 174 12 0x1002f450 (set (reg:SI 118)
(lshiftrt:SI (reg/v:SI 77)
(reg:SI 116))) 24 {lshrsi3} (insn_list 172 (nil))
(expr_list:REG_DEAD (reg:SI 116)
(nil)))
(insn 174 173 175 12 0x1002f450 (set (reg/v:SI 79)
(ior:SI (reg/v:SI 79)
(reg:SI 118))) 26 {iorsi3} (insn_list 173 (nil))
(expr_list:REG_DEAD (reg:SI 118)
(nil)))
(note 175 174 176 12 ("sqrt.c") 58)
(insn 176 175 177 12 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(reg/v:SI 84))) 22 {ashlsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 84)
(nil)))
;; End of basic block 12, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 13, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(code_label 177 176 474 13 8 "" [1 uses])
(note 474 177 178 13 [bb 13] NOTE_INSN_BASIC_BLOCK)
(note 178 474 179 13 ("sqrt.c") 60)
(insn 179 178 180 13 0x1002f450 (set (reg/v:SI 82)
(plus:SI (reg/v:SI 82)
(const_int -1023 [0xfffffc01]))) 12 {addsi3} (nil)
(nil))
(note 180 179 181 13 ("sqrt.c") 61)
(insn 181 180 182 13 0x1002f450 (set (reg/v:SI 79)
(and:SI (reg/v:SI 79)
(const_int 1048575 [0xfffff]))) 25 {andsi3} (nil)
(nil))
(insn 182 181 183 13 0x1002f450 (set (reg/v:SI 79)
(ior:SI (reg/v:SI 79)
(const_int 1048576 [0x100000]))) 26 {iorsi3} (insn_list 181 (nil))
(nil))
(note 183 182 184 13 ("sqrt.c") 62)
(insn 184 183 185 13 0x1002f450 (set (reg:SI 120)
(and:SI (reg/v:SI 82)
(const_int 1 [0x1]))) 25 {andsi3} (insn_list 179 (nil))
(nil))
(insn:QI 185 184 186 13 0x1002f450 (set (cc0)
(compare:SI (reg:SI 120)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 184 (nil))
(expr_list:REG_DEAD (reg:SI 120)
(nil)))
(jump_insn 186 185 189 13 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 196)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 13, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 189 186 475 ("sqrt.c") 64)
;; Start of basic block 14, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 475 189 190 14 [bb 14] NOTE_INSN_BASIC_BLOCK)
(note 190 475 191 14 NOTE_INSN_DELETED)
(insn 191 190 192 14 0x1002f450 (set (reg:SI 122)
(lshiftrt:SI (reg/v:SI 77)
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 192 191 193 14 0x1002f450 (set (reg:SI 123)
(plus:SI (reg/v:SI 79)
(reg:SI 122))) 12 {addsi3} (insn_list 191 (nil))
(expr_list:REG_DEAD (reg:SI 122)
(nil)))
(insn 193 192 194 14 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(reg:SI 123))) 12 {addsi3} (insn_list 192 (nil))
(expr_list:REG_DEAD (reg:SI 123)
(nil)))
(note 194 193 195 14 ("sqrt.c") 65)
(insn 195 194 196 14 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
;; End of basic block 14, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 15, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(code_label 196 195 476 15 18 "" [1 uses])
(note 476 196 197 15 [bb 15] NOTE_INSN_BASIC_BLOCK)
(note 197 476 198 15 ("sqrt.c") 67)
(insn 198 197 199 15 0x1002f450 (set (reg/v:SI 82)
(ashiftrt:SI (reg/v:SI 82)
(const_int 1 [0x1]))) 23 {ashrsi3} (nil)
(nil))
(note 199 198 200 15 ("sqrt.c") 70)
(note 200 199 201 15 NOTE_INSN_DELETED)
(insn 201 200 202 15 0x1002f450 (set (reg:SI 125)
(lshiftrt:SI (reg/v:SI 77)
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 202 201 203 15 0x1002f450 (set (reg:SI 126)
(plus:SI (reg/v:SI 79)
(reg:SI 125))) 12 {addsi3} (insn_list 201 (nil))
(expr_list:REG_DEAD (reg:SI 125)
(nil)))
(insn 203 202 204 15 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(reg:SI 126))) 12 {addsi3} (insn_list 202 (nil))
(expr_list:REG_DEAD (reg:SI 126)
(nil)))
(note 204 203 205 15 ("sqrt.c") 71)
(insn 205 204 206 15 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 206 205 207 15 ("sqrt.c") 72)
(insn 207 206 208 15 0x1002f450 (set (reg/v:SI 76)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 208 207 209 15 0x1002f450 (set (reg/v:SI 80)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 209 208 210 15 0x1002f450 (set (reg/v:SI 78)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn 210 209 211 15 0x1002f450 (set (reg/v:SI 81)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(note 211 210 212 15 ("sqrt.c") 73)
(insn 212 211 213 15 0x1002f450 (set (reg/v:SI 74)
(const_int 2097152 [0x200000])) 6 {*movsi} (nil)
(nil))
;; End of basic block 15, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 213 212 214 ("sqrt.c") 75)
(note 214 213 248 NOTE_INSN_LOOP_BEG)
;; Start of basic block 16, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(code_label 248 214 477 16 23 "" [1 uses])
(note 477 248 224 16 [bb 16] NOTE_INSN_BASIC_BLOCK)
(note 224 477 225 16 ("sqrt.c") 77)
(insn 225 224 226 16 0x1002f450 (set (reg/v:SI 83)
(plus:SI (reg/v:SI 80)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
(note 226 225 227 16 ("sqrt.c") 78)
(insn:QI 227 226 228 16 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 83)
(reg/v:SI 79))) 29 {cmpsi_internal} (insn_list 225 (nil))
(nil))
(jump_insn 228 227 231 16 0x1002f450 (set (pc)
(if_then_else (gt (cc0)
(const_int 0 [0x0]))
(label_ref 237)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 16, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 83 153
(note 231 228 478 ("sqrt.c") 80)
;; Start of basic block 17, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 81 82 83 153
(note 478 231 232 17 [bb 17] NOTE_INSN_BASIC_BLOCK)
(insn 232 478 233 17 0x1002f450 (set (reg/v:SI 80)
(plus:SI (reg/v:SI 83)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
(note 233 232 234 17 ("sqrt.c") 81)
(insn 234 233 235 17 0x1002f450 (set (reg/v:SI 79)
(minus:SI (reg/v:SI 79)
(reg/v:SI 83))) 13 {subsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 83)
(nil)))
(note 235 234 236 17 ("sqrt.c") 82)
(insn 236 235 237 17 0x1002f450 (set (reg/v:SI 81)
(plus:SI (reg/v:SI 81)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
;; End of basic block 17, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
;; Start of basic block 18, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(code_label 237 236 479 18 22 "" [1 uses])
(note 479 237 238 18 [bb 18] NOTE_INSN_BASIC_BLOCK)
(note 238 479 239 18 ("sqrt.c") 84)
(note 239 238 240 18 NOTE_INSN_DELETED)
(insn 240 239 241 18 0x1002f450 (set (reg:SI 128)
(lshiftrt:SI (reg/v:SI 77)
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 241 240 242 18 0x1002f450 (set (reg:SI 129)
(plus:SI (reg/v:SI 79)
(reg:SI 128))) 12 {addsi3} (insn_list 240 (nil))
(expr_list:REG_DEAD (reg:SI 128)
(nil)))
(insn 242 241 243 18 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(reg:SI 129))) 12 {addsi3} (insn_list 241 (nil))
(expr_list:REG_DEAD (reg:SI 129)
(nil)))
(note 243 242 244 18 ("sqrt.c") 85)
(insn 244 243 245 18 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 245 244 246 18 ("sqrt.c") 86)
(insn 246 245 247 18 0x1002f450 (set (reg/v:SI 74)
(lshiftrt:SI (reg/v:SI 74)
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(nil))
(note 247 246 542 18 NOTE_INSN_LOOP_CONT)
(note 542 247 216 18 NOTE_INSN_LOOP_VTOP)
(insn:QI 216 542 217 18 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 74)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 246 (nil))
(nil))
(jump_insn 217 216 253 18 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 248)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 18, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 253 217 255 NOTE_INSN_LOOP_END)
(note 255 253 483 ("sqrt.c") 89)
;; Start of basic block 19, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 76 77 78 79 80 81 82 153
(note 483 255 256 19 [bb 19] NOTE_INSN_BASIC_BLOCK)
(insn 256 483 257 19 0x1002f450 (set (reg/v:SI 74)
(const_int -2147483648 [0x80000000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int -2147483648 [0x80000000])
(nil)))
(note 257 256 585 19 ("sqrt.c") 90)
(insn 585 257 543 19 0x0 (set (reg/v:SI 73)
(const_int -2147483648 [0x80000000])) 6 {*movsi} (nil)
(expr_list:REG_EQUIV (const_int -2147483648 [0x80000000])
(nil)))
(insn:QI 543 585 544 19 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 73)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (nil)
(expr_list:REG_DEAD (reg/v:SI 73)
(expr_list:REG_EQUAL (compare:SI (const_int -2147483648 [0x80000000])
(const_int 0 [0x0]))
(nil))))
(jump_insn 544 543 258 19 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 545)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 3600 [0xe10])
(nil)))
;; End of basic block 19, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 258 544 328 NOTE_INSN_LOOP_BEG)
;; Start of basic block 20, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(code_label 328 258 484 20 33 "" [1 uses])
(note 484 328 268 20 [bb 20] NOTE_INSN_BASIC_BLOCK)
(note 268 484 269 20 ("sqrt.c") 92)
(insn 269 268 270 20 0x1002f450 (set (reg/v:SI 75)
(plus:SI (reg/v:SI 76)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
(note 270 269 271 20 ("sqrt.c") 93)
(insn 271 270 272 20 0x1002f450 (set (reg/v:SI 83)
(reg/v:SI 80)) 6 {*movsi} (nil)
(nil))
(note 272 271 273 20 ("sqrt.c") 94)
(insn:QI 273 272 274 20 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 83)
(reg/v:SI 79))) 29 {cmpsi_internal} (insn_list 271 (nil))
(nil))
(jump_insn 274 273 485 20 0x1002f450 (set (pc)
(if_then_else (lt (cc0)
(const_int 0 [0x0]))
(label_ref 290)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 20, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 21, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
(note 485 274 562 21 [bb 21] NOTE_INSN_BASIC_BLOCK)
(insn 562 485 563 21 0x1002f450 (set (reg:SI 164)
(xor:SI (reg/v:SI 83)
(reg/v:SI 79))) 27 {xorsi3} (nil)
(nil))
(insn 563 562 564 21 0x1002f450 (set (reg:SI 168)
(neg:SI (reg:SI 164))) 15 {negsi2} (insn_list 562 (nil))
(nil))
(insn 564 563 565 21 0x1002f450 (set (reg:SI 168)
(ior:SI (reg:SI 168)
(reg:SI 164))) 26 {iorsi3} (insn_list 563 (nil))
(expr_list:REG_DEAD (reg:SI 164)
(nil)))
(insn 565 564 566 21 0x1002f450 (set (reg:SI 168)
(not:SI (reg:SI 168))) 28 {one_cmplsi2} (insn_list 564 (nil))
(nil))
(note 566 565 567 21 NOTE_INSN_DELETED)
(insn 567 566 280 21 0x1002f450 (set (reg:SI 168)
(lshiftrt:SI (reg:SI 168)
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 565 (nil))
(nil))
(insn 280 567 281 21 0x1002f450 (set (reg:SI 131)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(nil))
(insn:QI 281 280 282 21 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 77)
(reg/v:SI 75))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 282 281 488 21 0x1002f450 (set (pc)
(if_then_else (ltu (cc0)
(const_int 0 [0x0]))
(label_ref 284)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 21, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
;; Start of basic block 22, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153 168
(note 488 282 283 22 [bb 22] NOTE_INSN_BASIC_BLOCK)
(insn 283 488 284 22 0x1002f450 (set (reg:SI 131)
(const_int 1 [0x1])) 6 {*movsi} (nil)
(insn_list:REG_WAS_0 280 (expr_list:REG_EQUAL (const_int 1 [0x1])
(nil))))
;; End of basic block 22, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
;; Start of basic block 23, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 131 153 168
(code_label 284 283 489 23 30 "" [1 uses])
(note 489 284 285 23 [bb 23] NOTE_INSN_BASIC_BLOCK)
(insn 285 489 286 23 0x1002f450 (set (reg:SI 168)
(and:SI (reg:SI 168)
(reg:SI 131))) 25 {andsi3} (nil)
(expr_list:REG_DEAD (reg:SI 131)
(nil)))
(insn:QI 286 285 287 23 0x1002f450 (set (cc0)
(compare:SI (reg:SI 168)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 285 (nil))
(expr_list:REG_DEAD (reg:SI 168)
(nil)))
(jump_insn 287 286 290 23 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 317)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 23, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 24, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 77 78 79 80 81 82 83 153
(code_label 290 287 491 24 28 "" [1 uses])
(note 491 290 293 24 [bb 24] NOTE_INSN_BASIC_BLOCK)
(note 293 491 294 24 ("sqrt.c") 96)
(insn 294 293 295 24 0x1002f450 (set (reg/v:SI 76)
(plus:SI (reg/v:SI 75)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
(note 295 294 296 24 ("sqrt.c") 97)
(insn 296 295 297 24 0x1002f450 (set (reg:SI 133)
(and:SI (reg/v:SI 75)
(const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil)
(nil))
(insn:QI 297 296 298 24 0x1002f450 (set (cc0)
(compare:SI (reg:SI 133)
(const_int -2147483648 [0x80000000]))) 29 {cmpsi_internal} (insn_list 296 (nil))
(expr_list:REG_DEAD (reg:SI 133)
(nil)))
(jump_insn 298 297 492 24 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 304)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 24, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
;; Start of basic block 25, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
(note 492 298 299 25 [bb 25] NOTE_INSN_BASIC_BLOCK)
(insn 299 492 568 25 0x1002f450 (set (reg:SI 134)
(and:SI (reg/v:SI 76)
(const_int -2147483648 [0x80000000]))) 25 {andsi3} (nil)
(nil))
(insn 568 299 569 25 0x1002f450 (set (reg:SI 170)
(neg:SI (reg:SI 134))) 15 {negsi2} (insn_list 299 (nil))
(nil))
(insn 569 568 570 25 0x1002f450 (set (reg:SI 170)
(ior:SI (reg:SI 170)
(reg:SI 134))) 26 {iorsi3} (insn_list 568 (nil))
(expr_list:REG_DEAD (reg:SI 134)
(nil)))
(insn 570 569 571 25 0x1002f450 (set (reg:SI 170)
(not:SI (reg:SI 170))) 28 {one_cmplsi2} (insn_list 569 (nil))
(nil))
(insn 571 570 573 25 0x1002f450 (set (reg:SI 170)
(lshiftrt:SI (reg:SI 170)
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 570 (nil))
(nil))
(insn 573 571 302 25 0x1002f450 (set (reg/v:SI 80)
(plus:SI (reg/v:SI 80)
(reg:SI 170))) 12 {addsi3} (insn_list 571 (nil))
(expr_list:REG_DEAD (reg:SI 170)
(nil)))
;; End of basic block 25, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
(note 302 573 304 ("sqrt.c") 98)
;; Start of basic block 26, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 83 153
(code_label 304 302 494 26 31 "" [1 uses])
(note 494 304 305 26 [bb 26] NOTE_INSN_BASIC_BLOCK)
(note 305 494 306 26 ("sqrt.c") 99)
(insn 306 305 307 26 0x1002f450 (set (reg/v:SI 79)
(minus:SI (reg/v:SI 79)
(reg/v:SI 83))) 13 {subsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 83)
(nil)))
(note 307 306 308 26 ("sqrt.c") 100)
(insn:QI 308 307 309 26 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 77)
(reg/v:SI 75))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 309 308 310 26 0x1002f450 (set (pc)
(if_then_else (geu (cc0)
(const_int 0 [0x0]))
(label_ref 312)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 26, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
(note 310 309 495 ("sqrt.c") 101)
;; Start of basic block 27, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
(note 495 310 311 27 [bb 27] NOTE_INSN_BASIC_BLOCK)
(insn 311 495 312 27 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(const_int -1 [0xffffffff]))) 12 {addsi3} (nil)
(nil))
;; End of basic block 27, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
;; Start of basic block 28, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 75 76 77 78 79 80 81 82 153
(code_label 312 311 496 28 32 "" [1 uses])
(note 496 312 313 28 [bb 28] NOTE_INSN_BASIC_BLOCK)
(note 313 496 314 28 ("sqrt.c") 102)
(insn 314 313 315 28 0x1002f450 (set (reg/v:SI 77)
(minus:SI (reg/v:SI 77)
(reg/v:SI 75))) 13 {subsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 75)
(nil)))
(note 315 314 316 28 ("sqrt.c") 103)
(insn 316 315 317 28 0x1002f450 (set (reg/v:SI 78)
(plus:SI (reg/v:SI 78)
(reg/v:SI 74))) 12 {addsi3} (nil)
(nil))
;; End of basic block 28, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
;; Start of basic block 29, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(code_label 317 316 497 29 27 "" [1 uses])
(note 497 317 318 29 [bb 29] NOTE_INSN_BASIC_BLOCK)
(note 318 497 319 29 ("sqrt.c") 105)
(note 319 318 320 29 NOTE_INSN_DELETED)
(insn 320 319 321 29 0x1002f450 (set (reg:SI 136)
(lshiftrt:SI (reg/v:SI 77)
(const_int 31 [0x1f]))) 24 {lshrsi3} (nil)
(nil))
(insn 321 320 322 29 0x1002f450 (set (reg:SI 137)
(plus:SI (reg/v:SI 79)
(reg:SI 136))) 12 {addsi3} (insn_list 320 (nil))
(expr_list:REG_DEAD (reg:SI 136)
(nil)))
(insn 322 321 323 29 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(reg:SI 137))) 12 {addsi3} (insn_list 321 (nil))
(expr_list:REG_DEAD (reg:SI 137)
(nil)))
(note 323 322 324 29 ("sqrt.c") 106)
(insn 324 323 325 29 0x1002f450 (set (reg/v:SI 77)
(ashift:SI (reg/v:SI 77)
(const_int 1 [0x1]))) 22 {ashlsi3} (nil)
(nil))
(note 325 324 326 29 ("sqrt.c") 107)
(insn 326 325 327 29 0x1002f450 (set (reg/v:SI 74)
(lshiftrt:SI (reg/v:SI 74)
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(nil))
(note 327 326 549 29 NOTE_INSN_LOOP_CONT)
(note 549 327 260 29 NOTE_INSN_LOOP_VTOP)
(insn:QI 260 549 261 29 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 74)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 326 (nil))
(nil))
(jump_insn 261 260 333 29 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 328)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 8900 [0x22c4])
(nil)))
;; End of basic block 29, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 74 76 77 78 79 80 81 82 153
(note 333 261 545 NOTE_INSN_LOOP_END)
;; Start of basic block 30, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 78 79 81 82 153
(code_label 545 333 501 30 52 "" [1 uses])
(note 501 545 335 30 [bb 30] NOTE_INSN_BASIC_BLOCK)
(note 335 501 336 30 ("sqrt.c") 111)
(insn 336 335 337 30 0x1002f450 (set (reg/v:SI 79)
(ior:SI (reg/v:SI 79)
(reg/v:SI 77))) 26 {iorsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 77)
(nil)))
(insn:QI 337 336 338 30 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 79)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 336 (nil))
(expr_list:REG_DEAD (reg/v:SI 79)
(nil)))
(jump_insn 338 337 341 30 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 408)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 30, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 341 338 502 ("sqrt.c") 113)
;; Start of basic block 31, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 502 341 342 31 [bb 31] NOTE_INSN_BASIC_BLOCK)
(insn 342 502 343 31 0x1002f450 (set (reg/v:DF 72)
(mem/u/f:DF (symbol_ref/u:SI ("*.LC0")) [2 S8 A32])) 10 {*movdf} (nil)
(expr_list:REG_EQUIV (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(nil)))
(note 343 342 344 31 ("sqrt.c") 114)
(note 344 343 345 31 NOTE_INSN_DELETED)
(insn 345 344 349 31 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 72)) 10 {*movdf} (insn_list 342 (nil))
(expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(insn_list:REG_LIBCALL 352 (nil))))
(insn 349 345 350 31 0x1002f450 (set (reg:SI 19 r19)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 350 349 351 31 0x1002f450 (set (reg:SI 0 r0)
(const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000])
(nil)))
(call_insn/u 351 350 352 31 0x1002f450 (parallel [
(set (reg:SI 18 r18)
(call (mem:QI (symbol_ref:SI ("__gedf2")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 350 (insn_list 349 (insn_list 345 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 19 r19)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 352 351 353 31 0x1002f450 (set (reg:SI 143)
(reg:SI 18 r18)) 6 {*movsi} (insn_list 351 (nil))
(expr_list:REG_DEAD (reg:SI 18 r18)
(insn_list:REG_RETVAL 345 (expr_list:REG_EQUAL (expr_list (reg/f:SI 139)
(expr_list (reg/v:DF 72)
(expr_list (reg/v:DF 72)
(nil))))
(nil)))))
(insn:QI 353 352 354 31 0x1002f450 (set (cc0)
(compare:SI (reg:SI 143)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 352 (nil))
(expr_list:REG_DEAD (reg:SI 143)
(nil)))
(jump_insn 354 353 360 31 0x1002f450 (set (pc)
(if_then_else (lt (cc0)
(const_int 0 [0x0]))
(label_ref 408)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 2100 [0x834])
(nil)))
;; End of basic block 31, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(note 360 354 362 ("sqrt.c") 116)
(note 362 360 504 ("sqrt.c") 117)
;; Start of basic block 32, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(note 504 362 363 32 [bb 32] NOTE_INSN_BASIC_BLOCK)
(insn:QI 363 504 364 32 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 78)
(const_int -1 [0xffffffff]))) 29 {cmpsi_internal} (nil)
(nil))
(jump_insn 364 363 367 32 0x1002f450 (set (pc)
(if_then_else (ne (cc0)
(const_int 0 [0x0]))
(label_ref 373)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 7100 [0x1bbc])
(nil)))
;; End of basic block 32, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(note 367 364 505 ("sqrt.c") 119)
;; Start of basic block 33, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 81 82 153
(note 505 367 368 33 [bb 33] NOTE_INSN_BASIC_BLOCK)
(insn 368 505 369 33 0x1002f450 (set (reg/v:SI 78)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(note 369 368 370 33 ("sqrt.c") 120)
(insn 370 369 371 33 0x1002f450 (set (reg/v:SI 81)
(plus:SI (reg/v:SI 81)
(const_int 1 [0x1]))) 12 {addsi3} (nil)
(nil))
(jump_insn 371 370 372 33 0x1002f450 (set (pc)
(label_ref 408)) 35 {jump} (nil)
(nil))
;; End of basic block 33, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(barrier 372 371 373)
;; Start of basic block 34, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 72 78 81 82 153
(code_label 373 372 506 34 37 "" [1 uses])
(note 506 373 374 34 [bb 34] NOTE_INSN_BASIC_BLOCK)
(note 374 506 375 34 ("sqrt.c") 122)
(note 375 374 376 34 NOTE_INSN_DELETED)
(insn 376 375 380 34 0x1002f450 (set (reg:DF 17 r17)
(reg/v:DF 72)) 10 {*movdf} (nil)
(expr_list:REG_DEAD (reg/v:DF 72)
(expr_list:REG_EQUAL (const_double:DF -2147483648 [0x80000000] 1.0e+0 [0x0.8p+1])
(insn_list:REG_LIBCALL 383 (nil)))))
(insn 380 376 381 34 0x1002f450 (set (reg:SI 19 r19)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 381 380 382 34 0x1002f450 (set (reg:SI 0 r0)
(const_int 1072693248 [0x3ff00000])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 1072693248 [0x3ff00000])
(nil)))
(call_insn/u 382 381 383 34 0x1002f450 (parallel [
(set (reg:SI 18 r18)
(call (mem:QI (symbol_ref:SI ("__gtdf2")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 381 (insn_list 380 (insn_list 376 (nil))))
(expr_list:REG_DEAD (reg:SI 17 r17)
(expr_list:REG_DEAD (reg:SI 19 r19)
(expr_list:REG_DEAD (reg:SI 0 r0)
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_EH_REGION (const_int -1 [0xffffffff])
(nil))))))
(expr_list (use (reg:SI 0 r0))
(expr_list (use (reg:SI 19 r19))
(expr_list (use (reg:DF 17 r17))
(nil)))))
(insn 383 382 384 34 0x1002f450 (set (reg:SI 148)
(reg:SI 18 r18)) 6 {*movsi} (insn_list 382 (nil))
(expr_list:REG_DEAD (reg:SI 18 r18)
(insn_list:REG_RETVAL 376 (expr_list:REG_EQUAL (expr_list (reg/f:SI 144)
(expr_list (reg/v:DF 72)
(expr_list (reg/v:DF 72)
(nil))))
(nil)))))
(insn:QI 384 383 385 34 0x1002f450 (set (cc0)
(compare:SI (reg:SI 148)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 383 (nil))
(expr_list:REG_DEAD (reg:SI 148)
(nil)))
(jump_insn 385 384 391 34 0x1002f450 (set (pc)
(if_then_else (le (cc0)
(const_int 0 [0x0]))
(label_ref 401)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 2100 [0x834])
(nil)))
;; End of basic block 34, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 391 385 508 ("sqrt.c") 124)
;; Start of basic block 35, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(note 508 391 574 35 [bb 35] NOTE_INSN_BASIC_BLOCK)
(insn 574 508 575 35 0x1002f450 (set (reg:SI 176)
(xor:SI (reg/v:SI 78)
(const_int -2 [0xfffffffe]))) 27 {xorsi3} (nil)
(nil))
(insn 575 574 576 35 0x1002f450 (set (reg:SI 177)
(neg:SI (reg:SI 176))) 15 {negsi2} (insn_list 574 (nil))
(nil))
(insn 576 575 577 35 0x1002f450 (set (reg:SI 177)
(ior:SI (reg:SI 177)
(reg:SI 176))) 26 {iorsi3} (insn_list 575 (nil))
(expr_list:REG_DEAD (reg:SI 176)
(nil)))
(insn 577 576 578 35 0x1002f450 (set (reg:SI 177)
(not:SI (reg:SI 177))) 28 {one_cmplsi2} (insn_list 576 (nil))
(nil))
(insn 578 577 580 35 0x1002f450 (set (reg:SI 177)
(lshiftrt:SI (reg:SI 177)
(const_int 31 [0x1f]))) 24 {lshrsi3} (insn_list 577 (nil))
(nil))
(insn 580 578 394 35 0x1002f450 (set (reg/v:SI 81)
(plus:SI (reg/v:SI 81)
(reg:SI 177))) 12 {addsi3} (insn_list 578 (nil))
(expr_list:REG_DEAD (reg:SI 177)
(nil)))
(note 394 580 397 35 ("sqrt.c") 125)
(note 397 394 398 35 ("sqrt.c") 126)
(insn 398 397 399 35 0x1002f450 (set (reg/v:SI 78)
(plus:SI (reg/v:SI 78)
(const_int 2 [0x2]))) 12 {addsi3} (nil)
(nil))
(jump_insn 399 398 400 35 0x1002f450 (set (pc)
(label_ref 408)) 35 {jump} (nil)
(nil))
;; End of basic block 35, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(barrier 400 399 401)
;; Start of basic block 36, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(code_label 401 400 511 36 39 "" [1 uses])
(note 511 401 402 36 [bb 36] NOTE_INSN_BASIC_BLOCK)
(note 402 511 403 36 ("sqrt.c") 129)
(insn 403 402 404 36 0x1002f450 (set (reg:SI 149)
(and:SI (reg/v:SI 78)
(const_int 1 [0x1]))) 25 {andsi3} (nil)
(nil))
(insn 404 403 408 36 0x1002f450 (set (reg/v:SI 78)
(plus:SI (reg/v:SI 78)
(reg:SI 149))) 12 {addsi3} (insn_list 403 (nil))
(expr_list:REG_DEAD (reg:SI 149)
(nil)))
;; End of basic block 36, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
;; Start of basic block 37, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 78 81 82 153
(code_label 408 404 515 37 34 "" [4 uses])
(note 515 408 409 37 [bb 37] NOTE_INSN_BASIC_BLOCK)
(note 409 515 410 37 ("sqrt.c") 132)
(insn 410 409 411 37 0x1002f450 (set (reg/v:SI 79)
(ashiftrt:SI (reg/v:SI 81)
(const_int 1 [0x1]))) 23 {ashrsi3} (nil)
(nil))
(insn 411 410 412 37 0x1002f450 (set (reg/v:SI 79)
(plus:SI (reg/v:SI 79)
(const_int 1071644672 [0x3fe00000]))) 12 {addsi3} (insn_list 410 (nil))
(nil))
(note 412 411 413 37 ("sqrt.c") 133)
(insn 413 412 414 37 0x1002f450 (set (reg/v:SI 77)
(lshiftrt:SI (reg/v:SI 78)
(const_int 1 [0x1]))) 24 {lshrsi3} (nil)
(expr_list:REG_DEAD (reg/v:SI 78)
(nil)))
(note 414 413 415 37 ("sqrt.c") 134)
(insn 415 414 416 37 0x1002f450 (set (reg/v:SI 81)
(and:SI (reg/v:SI 81)
(const_int 1 [0x1]))) 25 {andsi3} (nil)
(nil))
(insn:QI 416 415 417 37 0x1002f450 (set (cc0)
(compare:SI (reg/v:SI 81)
(const_int 0 [0x0]))) 29 {cmpsi_internal} (insn_list 415 (nil))
(expr_list:REG_DEAD (reg/v:SI 81)
(nil)))
(jump_insn 417 416 418 37 0x1002f450 (set (pc)
(if_then_else (eq (cc0)
(const_int 0 [0x0]))
(label_ref 420)
(pc))) 31 {branch_internal} (nil)
(expr_list:REG_BR_PROB (const_int 5000 [0x1388])
(nil)))
;; End of basic block 37, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 418 417 516 ("sqrt.c") 135)
;; Start of basic block 38, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(note 516 418 419 38 [bb 38] NOTE_INSN_BASIC_BLOCK)
(insn 419 516 420 38 0x1002f450 (set (reg/v:SI 77)
(ior:SI (reg/v:SI 77)
(const_int -2147483648 [0x80000000]))) 26 {iorsi3} (nil)
(nil))
;; End of basic block 38, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
;; Start of basic block 39, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 77 79 82 153
(code_label 420 419 517 39 43 "" [1 uses])
(note 517 420 421 39 [bb 39] NOTE_INSN_BASIC_BLOCK)
(note 421 517 422 39 ("sqrt.c") 136)
(insn 422 421 423 39 0x1002f450 (set (reg/v:SI 82)
(ashift:SI (reg/v:SI 82)
(const_int 20 [0x14]))) 22 {ashlsi3} (nil)
(nil))
(note 423 422 427 39 NOTE_INSN_DELETED)
(note 427 423 428 39 ("sqrt.c") 139)
(note 428 427 429 39 ("sqrt.c") 140)
(insn 429 428 430 39 0x1002f420 (set (subreg:SI (reg/v:DI 153) 4)
(plus:SI (reg/v:SI 79)
(reg/v:SI 82))) 12 {addsi3} (insn_list 422 (nil))
(expr_list:REG_DEAD (reg/v:SI 82)
(expr_list:REG_DEAD (reg/v:SI 79)
(nil))))
(note 430 429 431 39 ("sqrt.c") 141)
(insn 431 430 432 39 0x1002f420 (set (subreg:SI (reg/v:DI 153) 0)
(reg/v:SI 77)) 6 {*movsi} (insn_list 429 (nil))
(expr_list:REG_DEAD (reg/v:SI 77)
(nil)))
(note 432 431 433 39 ("sqrt.c") 142)
(insn 433 432 436 39 0x1002f420 (set (reg:DF 70)
(subreg:DF (reg/v:DI 153) 0)) 10 {*movdf} (insn_list 431 (nil))
(expr_list:REG_DEAD (reg/v:DI 153)
(nil)))
(note 436 433 443 39 ("sqrt.c") 145)
;; End of basic block 39, registers live:
20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(note 443 436 444 NOTE_INSN_FUNCTION_END)
(note 444 443 445 ("sqrt.c") 146)
;; Start of basic block 40, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap] 70
(code_label 445 444 520 40 1 "" [3 uses])
(note 520 445 446 40 [bb 40] NOTE_INSN_BASIC_BLOCK)
(insn 446 520 449 40 0x1002f480 (set (reg/i:DF 18 r18)
(reg:DF 70)) 10 {*movdf} (nil)
(expr_list:REG_DEAD (reg:DF 70)
(nil)))
(insn 449 446 0 40 0x1002f480 (use (reg/i:DF 18 r18)) -1 (insn_list 446 (nil))
(nil))
;; End of basic block 40, registers live:
18 [r18] 19 [r19] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
;; Function main
Pass 0
Register 71 costs: ADDR8_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:0 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:4000 MEM:10000
Register 73 costs: ADDR8_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:0 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:4000 MEM:10000
Register 71 pref ADDR32_REGS
Register 73 pref ADDR32_REGS
Pass 1
Register 71 costs: ADDR8_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:0 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:4000 MEM:10000
Register 73 costs: ADDR8_REGS:2000 ADDR16_REGS:2000 EVEN_REGS:2000 ADDR32_REGS:0 DATA_REGS:2000 GPR_REGS:2000 ALL_REGS:4000 MEM:10000
75 registers.
Register 73 used 2 times across 2 insns in block 0; set 1 time; 8 bytes; pref ADDR32_REGS.
1 basic blocks, 2 edges.
Basic block 0: first insn 27, last 26, prev -1, next -2, loop_depth 0, count 0, freq 10000, maybe hot.
Predecessors: ENTRY [100.0%] (fallthru)
Successors: EXIT [100.0%] (fallthru)
Registers live at start: 20 [r20] 21 [r21] 30 [r30] 64 [ap]
Registers live at end: 18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
;; Register 73 in 18.
(note 1 0 3 ("sqrt.c") 151)
(note 3 1 7 NOTE_INSN_FUNCTION_BEG)
(note 7 3 27 ("sqrt.c") 152)
;; Start of basic block 0, registers live: 20 [r20] 21 [r21] 30 [r30] 64 [ap]
(note 27 7 9 0 [bb 0] NOTE_INSN_BASIC_BLOCK)
(note 9 27 10 0 NOTE_INSN_DELETED)
(insn 10 9 11 0 0x0 (set (reg:DF 17 r17)
(mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])) 10 {*movdf} (insn_list 8 (nil))
(nil))
(call_insn 11 10 12 0 0x0 (parallel [
(set (reg:DF 18 r18)
(call (mem:QI (symbol_ref:SI ("__ieee754_sqrt")) [0 S1 A8])
(const_int 0 [0x0])))
(use (const_int 0 [0x0]))
(clobber (reg:SI 16 r16))
]) 33 {call_value_internal} (insn_list 10 (nil))
(expr_list:REG_EH_REGION (const_int 0 [0x0])
(expr_list:REG_UNUSED (reg:SI 16 r16)
(expr_list:REG_DEAD (reg:SI 17 r17)
(nil))))
(expr_list (use (reg:DF 17 r17))
(nil)))
(insn 12 11 13 0 0x0 (set (reg:DF 73)
(reg:DF 18 r18)) 10 {*movdf} (insn_list 11 (nil))
(expr_list:REG_EQUIV (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
(expr_list:REG_DEAD (reg:DF 18 r18)
(nil))))
(insn 13 12 14 0 0x0 (set (mem/f:DF (symbol_ref:SI ("%c")) [2 c+0 S8 A32])
(reg:DF 73)) 10 {*movdf} (insn_list 12 (nil))
(expr_list:REG_DEAD (reg:DF 73)
(nil)))
(note 14 13 20 0 ("sqrt.c") 154)
(note 20 14 21 0 NOTE_INSN_FUNCTION_END)
(note 21 20 23 0 ("sqrt.c") 155)
(insn 23 21 26 0 0x0 (set (reg/i:SI 18 r18)
(const_int 0 [0x0])) 6 {*movsi} (nil)
(expr_list:REG_EQUAL (const_int 0 [0x0])
(nil)))
(insn 26 23 0 0 0x0 (use (reg/i:SI 18 r18)) -1 (insn_list 23 (nil))
(nil))
;; End of basic block 0, registers live:
18 [r18] 20 [r20] 21 [r21] 30 [r30] 64 [ap]
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-30 15:28 ` Sanjiv Kumar Gupta
@ 2005-05-31 12:13 ` Sanjiv Kumar Gupta
0 siblings, 0 replies; 8+ messages in thread
From: Sanjiv Kumar Gupta @ 2005-05-31 12:13 UTC (permalink / raw)
To: Sanjiv Kumar Gupta; +Cc: Ian Lance Taylor, gcc
. I don't know whether gcc mail server
> accepts attachments or not,
>
Oh. It does.
> --- Ian Lance Taylor <ian@airs.com> wrote:
>
>
>>Sanjiv Kumar Gupta <skgnu@yahoo.com> writes:
>>
>>
>>>I am using gcc 3.3.1 release as my port, and looks
>>>like I have hit a problem with greg.
>>
>>You neglected to mention what target you are using.
>>
>>
>>>I couldn't understand why the insns 620 and 621
>>
>>are
>>
>>>being generated here as DI moves.
>>
>>I'm not sure specifically why it got a DI move here,
>>but it doesn't
>>look wrong. It's treating the struct named parts as
>>DImode.
>>
>>
>>>This is creating problem since insn 621 gets
>>
>>splitted
>>
>>>after reload into two SI moves,i.e. @(r21, -8) and
>>>@(r21, -4).
>>>This renders insns 619 as dead and hence insns 618
>>
>>and
>>
>>>insn 429 as dead, which are eliminated by flow2.
>>
>>It does look rather suspicious, but it's hard to
>>know whether it is
>>wrong without seeing the value in r1.
>>
>>Does the behaviour change if you use
>>-fno-strict-aliasing? (I can't
>>remember what the default was in 3.3.1).
>>
>>Ian
>>
>
>
>
>
> __________________________________
> Yahoo! Mail
> Stay connected, organized, and protected. Take the tour:
> http://tour.mail.yahoo.com/mailtour.html
^ permalink raw reply [flat|nested] 8+ messages in thread
* RE: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-30 15:28 ` Sanjiv Kumar Gupta
@ 2005-06-02 13:19 ` Dave Korn
2005-06-04 2:58 ` Ian Lance Taylor
1 sibling, 0 replies; 8+ messages in thread
From: Dave Korn @ 2005-06-02 13:19 UTC (permalink / raw)
To: 'Sanjiv Kumar Gupta', 'Ian Lance Taylor'
Cc: 'Sanjiv Kumar Gupta', gcc
----Original Message----
>From: Sanjiv Kumar Gupta
>Sent: 30 May 2005 14:55
> Ian Lance Taylor wrote:
>
>> Sanjiv Kumar Gupta <skgnu@yahoo.com> writes:
>>
>>
>>> I am using gcc 3.3.1 release as my port, and looks
>>> like I have hit a problem with greg.
>>
>>
>> You neglected to mention what target you are using.
>>
> Ian, the port is for a 32-bit RISC and not complete yet,
> hence still not contributed.
> This probably makes difficult for you to suggest any
> fix, but I still asked in case I could get any pointers
> for investigation.
Does your port implement the movdi pattern? You can get bad interactions
when gcc tries to implement blkmode moves using dimode moves if movdi
doesn't exist in your .md file. If your target doesn't have a natural
DImode move instruction, use a define_expand to separate it into two movsi
insns.
cheers,
DaveK
--
Can't think of a witty .sigline today....
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-06-02 13:19 ` Dave Korn
@ 2005-06-04 2:58 ` Ian Lance Taylor
2005-06-17 12:55 ` Sanjiv Kumar Gupta
1 sibling, 1 reply; 8+ messages in thread
From: Ian Lance Taylor @ 2005-06-04 2:58 UTC (permalink / raw)
To: Sanjiv Kumar Gupta; +Cc: Sanjiv Kumar Gupta, gcc
Sanjiv Kumar Gupta <sanjiv.gupta@oracle.com> writes:
> >>I couldn't understand why the insns 620 and 621 are
> >>being generated here as DI moves.
> > I'm not sure specifically why it got a DI move here, but it doesn't
> > look wrong. It's treating the struct named parts as DImode.
> >
> >>This is creating problem since insn 621 gets splitted
> >>after reload into two SI moves,i.e. @(r21, -8) and
> >>@(r21, -4).
> >>This renders insns 619 as dead and hence insns 618 and
> >>insn 429 as dead, which are eliminated by flow2.
> > It does look rather suspicious, but it's hard to know whether it is
> > wrong without seeing the value in r1.
> >
> r1 looks unrelated to struct members, and is being used by the
> ifcvt pass to expand some comparison insns.
In your .23 file, this is insn 431:
(insn 431 430 432 39 0x1002f420 (set (subreg:SI (reg/v:DI 153) 0)
(reg/v:SI 77)) 6 {*movsi} (insn_list 429 (nil))
(expr_list:REG_DEAD (reg/v:SI 77)
(nil)))
So it is setting the first SI subreg of a DI value. reload decides to
do an output reload for register 153. Since register 153 is DImode,
it does a DImode reload.
It winds up copying the DImode value to r2, and then writing r2 to
memory. The double move is because there is a secondary reload
involved. That implies that SECONDARY_OUTPUT_RELOAD_CLASS is defined
and is returning something other than NO_REGS for this case.
I see that insn 429 is setting the high part of register 153. Insn
429 looks like this:
(insn 429 428 430 39 0x1002f420 (set (subreg:SI (reg/v:DI 153) 4)
(plus:SI (reg/v:SI 79)
(reg/v:SI 82))) 12 {addsi3} (insn_list 422 (nil))
(expr_list:REG_DEAD (reg/v:SI 82)
(expr_list:REG_DEAD (reg/v:SI 79)
(nil))))
But note that a set to a subreg is explicitly defined to set the other
parts of the register to garbage. Therefore the value set by insn 429
is destroyed by insn 431.
I would guess that you need a strict_low_part in insns 429 and 431.
See the RTL documentation.
Ian
^ permalink raw reply [flat|nested] 8+ messages in thread
* Re: GCC 3.3.1 -O2 problem with sqrt.c
2005-06-04 2:58 ` Ian Lance Taylor
@ 2005-06-17 12:55 ` Sanjiv Kumar Gupta
0 siblings, 0 replies; 8+ messages in thread
From: Sanjiv Kumar Gupta @ 2005-06-17 12:55 UTC (permalink / raw)
To: Ian Lance Taylor, Sanjiv Kumar Gupta; +Cc: Sanjiv Kumar Gupta, gcc
--- Ian Lance Taylor <ian@airs.com> wrote:
> Sanjiv Kumar Gupta <sanjiv.gupta@oracle.com> writes:
>
> > >>I couldn't understand why the insns 620 and 621
> are
> > >>being generated here as DI moves.
> > > I'm not sure specifically why it got a DI move
> here, but it doesn't
> > > look wrong. It's treating the struct named
> parts as DImode.
> > >
> > >>This is creating problem since insn 621 gets
> splitted
> > >>after reload into two SI moves,i.e. @(r21, -8)
> and
> > >>@(r21, -4).
> > >>This renders insns 619 as dead and hence insns
> 618 and
> > >>insn 429 as dead, which are eliminated by flow2.
> > > It does look rather suspicious, but it's hard to
> know whether it is
> > > wrong without seeing the value in r1.
> > >
> > r1 looks unrelated to struct members, and is being
> used by the
> > ifcvt pass to expand some comparison insns.
>
> In your .23 file, this is insn 431:
>
> (insn 431 430 432 39 0x1002f420 (set (subreg:SI
> (reg/v:DI 153) 0)
> (reg/v:SI 77)) 6 {*movsi} (insn_list 429
> (nil))
> (expr_list:REG_DEAD (reg/v:SI 77)
> (nil)))
>
> So it is setting the first SI subreg of a DI value.
> reload decides to
> do an output reload for register 153. Since
> register 153 is DImode,
> it does a DImode reload.
>
> It winds up copying the DImode value to r2, and then
> writing r2 to
> memory. The double move is because there is a
> secondary reload
> involved. That implies that
> SECONDARY_OUTPUT_RELOAD_CLASS is defined
> and is returning something other than NO_REGS for
> this case.
>
> I see that insn 429 is setting the high part of
> register 153. Insn
> 429 looks like this:
>
> (insn 429 428 430 39 0x1002f420 (set (subreg:SI
> (reg/v:DI 153) 4)
> (plus:SI (reg/v:SI 79)
> (reg/v:SI 82))) 12 {addsi3} (insn_list
> 422 (nil))
> (expr_list:REG_DEAD (reg/v:SI 82)
> (expr_list:REG_DEAD (reg/v:SI 79)
> (nil))))
>
> But note that a set to a subreg is explicitly
> defined to set the other
> parts of the register to garbage. Therefore the
> value set by insn 429
> is destroyed by insn 431.
>
> I would guess that you need a strict_low_part in
> insns 429 and 431.
> See the RTL documentation.
>
> Ian
>
Thanks Ian for your inputs. The problem got solved.
There was no intermediate reg needed for this reload.
But I still feel that a strict_low_part would be
needed as you suggested.
Thanks again.
Sanjiv
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^ permalink raw reply [flat|nested] 8+ messages in thread
end of thread, other threads:[~2005-06-17 12:55 UTC | newest]
Thread overview: 8+ messages (download: mbox.gz / follow: Atom feed)
-- links below jump to the message on this page --
2005-05-27 13:42 GCC 3.3.1 -O2 problem with sqrt.c Sanjiv Kumar Gupta
2005-05-27 17:49 ` Ian Lance Taylor
2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-05-31 12:13 ` Sanjiv Kumar Gupta
2005-05-30 15:28 ` Sanjiv Kumar Gupta
2005-06-02 13:19 ` Dave Korn
2005-06-04 2:58 ` Ian Lance Taylor
2005-06-17 12:55 ` Sanjiv Kumar Gupta
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