From mboxrd@z Thu Jan 1 00:00:00 1970 Return-Path: Received: (qmail 600 invoked by alias); 16 Feb 2006 00:46:19 -0000 Received: (qmail 590 invoked by uid 22791); 16 Feb 2006 00:46:19 -0000 X-Spam-Check-By: sourceware.org Received: from mx1.redhat.com (HELO mx1.redhat.com) (66.187.233.31) by sourceware.org (qpsmtpd/0.31) with ESMTP; Thu, 16 Feb 2006 00:46:18 +0000 Received: from int-mx1.corp.redhat.com (int-mx1.corp.redhat.com [172.16.52.254]) by mx1.redhat.com (8.12.11/8.12.11) with ESMTP id k1G0kDVG014049; Wed, 15 Feb 2006 19:46:13 -0500 Received: from post-office.corp.redhat.com (post-office.corp.redhat.com [172.16.52.227]) by int-mx1.corp.redhat.com (8.11.6/8.11.6) with ESMTP id k1G0k8109451; Wed, 15 Feb 2006 19:46:08 -0500 Received: from greed.delorie.com (dj.cipe.redhat.com [10.0.0.222]) by post-office.corp.redhat.com (8.11.6/8.11.6) with ESMTP id k1G0k6t09369; Wed, 15 Feb 2006 19:46:06 -0500 Received: from greed.delorie.com (greed.delorie.com [127.0.0.1]) by greed.delorie.com (8.13.1/8.13.1) with ESMTP id k1G0k3bp025676; Wed, 15 Feb 2006 19:46:03 -0500 Received: (from dj@localhost) by greed.delorie.com (8.13.1/8.13.1/Submit) id k1G0jwRV025673; Wed, 15 Feb 2006 19:45:58 -0500 Date: Thu, 16 Feb 2006 00:46:00 -0000 Message-Id: <200602160045.k1G0jwRV025673@greed.delorie.com> From: DJ Delorie To: tnt@246tNt.com CC: gcc@gcc.gnu.org In-reply-to: <43F3C6F8.7080007@246tNt.com> (message from Sylvain Munaut on Thu, 16 Feb 2006 01:27:36 +0100) Subject: Re: Design a microcontroller for gcc References: <43F2666E.70703@246tNt.com> <43F3C6F8.7080007@246tNt.com> X-IsSubscribed: yes Mailing-List: contact gcc-help@gcc.gnu.org; run by ezmlm Precedence: bulk List-Archive: List-Post: List-Help: Sender: gcc-owner@gcc.gnu.org X-SW-Source: 2006-02/txt/msg00275.txt.bz2 > What's so bad about have the flag as side-effects ? You can't put any other insn between the compare and the jump. Like, if you wanted to move an address into a register to do the jump, you'd lose the condition bits. The advantage of having most insns set flags, is you can sometimes avoid the compare completely. > MIPS has no flag ??? how does branching work ? Some chips combine the compare and jump into one insn, like "jeq $r0,4,label". > Or maybe just allow immediates in the mov but that seems like a big > penalty ... Most risc chips have more move insns than other opcodes. So, you'd have two adds (register and sign- or zero-extended immediate), and a variety of moves (lower, upper, extended, etc). You have to think about what kind of constants are going to be common in your software, and plan accordingly.